Sony CDX-C90 Service Manual page 49

Fm/am compact disc player
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• IC501 CXD2548R (DIGITAL SERVO, DIGITAL SIGNAL PROCESSOR)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
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L 13942296513
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
www
47
48
49
.
50
51
52
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Pin Name
I/O
SYSM
I
System mute input (Not used.)
RMUT1
O
R-ch, "0" detection output. ("H" : ON, "L" : OFF) (Not used.)
LMUT2
O
L-ch, "0" detection output. ("H" : ON, "L" : OFF) (Not used.)
CKOUT
O
Master clock frequency division output (Not used.)
VDD0
Digital power supply
SBSO
O
Serial output of sub-P to W.
EXCK
I
Clock input for SBSO read output.
SQCK
I
Clock input for SQSO read output.
SQSO
O
SubQ 80 bit, PCM peak and level data 16 bit output.
SENS
O
SENS output. Output to CPU.
SCLK
I
Clock input for SENS real data read.
DATA
I
Serial data input from CPU.
XLAT
I
Latch input from CPU. Latch serial data at the falling edge.
CLOK
I
Serial data transfer clock input from CPU.
XRST
I
System reset ("L" : Reset)
ACDT
O
Not used.
PWM1
I
External control input of spindle motor.
XLON
O
Microcomputer extension interface (Output) (Not used.)
SPOA
I
Microcomputer extension interface (Input A) (Not used.)
WFCK
O
WFCK (Write Flame Clock) output
GTOP
O
GTOP output
XUGF
O
XUGF output (Not used.)
XPCK
O
XPLCK output (Not used.)
GFS
O
GFS output
RFCK
O
RFCK output
C2PO
O
C2PO output (Not used.)
XROF
O
XROF output
SCOR
O
"H" output at either detection, sub code sync S0 or S1.
MNT0
O
MNT0 output (Not used.)
MNT1
O
MNT1 output (Not used.)
MNT3
O
MNT3 output (Not used.)
VSS1
Digital GND
DOUT
O
Digital-Out output
ATSK
I
For anti-shock.
MIRR
O
Mirror signal output (Not used.)
DFCT
O
Diffect signal output (Not used.)
FOK
O
Focus OK signal output
VDD1
Digital power supply
VPCO1
O
Charge pump output for wideband EFM PLL.
VPCO2
O
VCO2 charge pump output for wideband EFM PLL.
VCK.I
I
VCO2 oscillator input for wideband EFM PLL.
V16M
O
VCO2 oscillator output for wideband EFM PLL.
VCTL
I
VCO2 control input for wideband EFM PLL.
PCO
O
Charge pump output for master PLL.
FILO
O
Filter output for master PLL (Slave = digital PLL).
FILI
I
Filter input for master PLL.
AVSS4
Analog GND
x
ao
CLTV
I
y
VCO control voltage input for master.
AVDD4
Analog power supply
i
RFAC
I
EFM signal input
BIAS
I
Asymmetry circuit constant current input
ASY.I
I
Asymmetry comparate voltage input
http://www.xiaoyu163.com
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2 9
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Pin Description
1 5
0 5
8
2 9
9 4
m
co
9 9
2 8
9 9

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