Ic Pin Function Description - Sony SPP-SS964 Service Manual

• IC Block Diagrams
IC103 MC34118DW (BASE MAIN BOARD)
28 27 26 25 24 23 22 21
RX
ATTEN- DIAL
UATOR TONE
DETECTOR
BACKGROUND BACKGROUND
LEVEL
NOISE NOISE
DETECTOR
DETECTOR DETECTOR
LEVEL COMPARATOR COMPARATOR
DETECTOR
VCC AGC
HYBRID HYBRID
VR VR
ATTENUATOR
AMP 2 AMP 1
+
FILTER
+
AMP
–
–
2 3 4 5
1 6 7 8
IC401 10497-15 (HAND MAIN BOARD)
IC701 10497-15 (BASE MAIN BOARD)
24 23 22 21 20 19 18 17
16
16 BIT MODULATOR
25
RESETB
15
REGISTOR & FILTER
MCLK 26
14
DVSS 27
13
CONTROL
DVDD
28
REGISTOR
DATAI 29
12
30
DATAO
16 BIT MODULATOR
11
NC 31
REGISTOR
& FILTER
10
NC 32
9
1 2 3 4 5 6 7 8
IC104 MC34119DR2 (BASE MAIN BOARD)
20 19 18 17 16 15
8 7 6
VREF
BIAS
CIRCUIT
LEVEL
DETECTOR
1 2
LEVEL
DETECTOR
MIC
TX
VR
AMP
+
–
9 10 12 14
11 13
IC502 S-24C16AFJ-TB (HAND MAIN BOARD)
IC951 S-24C02AFJ-TB (BASE MAIN BOARD)
VCC TEST INPUT SCL
8 7 6
START CYCLE
START
STOP
VOXRNT
LOGIC
VOXSND
CONTROL
AVDD
LOGIC
LINE-IN
XDEC
32
AVSS
LOAD
INC
MICIN
WORD
RBIAS
ADDRESS
NC
COUNTER
5
2
R/W
CK
PIN
D
OUT
ACK
1 2 3
NC NC NC
– 47 –

7-13. IC PIN FUNCTION DESCRIPTION

• HAND MAIN BOARD IC501 M7012-11 (ASIC)
Pin No. Pin Name
1 KEYPADB5
5
2 D0
3, 4 D1, D2
5 D3
6 to 9 D4 to D7
+ KEYPADI0 to
10 to 15
_
KEYPADI5
16 VSSC
3 4
17 VDDC
18 VDDP
19 VSSC
20 OSCI
21 OSCO
22
KEYPADB3
23
KEYPADB4
24 CDCDATAI
25 CDCDATAO
26 CDCMCLK
27 RESETO
28 CDCICLK
29 VDDP
30 VSSP
31 KEYPADB2
32 CDCFRAME
33 ARTI
SDA
5
34 ARTO
KEYPADB1,
35, 36
KEYPADB0
37 GPIOB7
H.V. GENERATION
TIMING
38 VDDP
& CONTROL
39 LCDCS
40 VDDC
E PROM 2
41 VSSC
32 x 32
42 TEST
43 LNAATN
32
44 RXEN
45 VDDA
YDEC
46 VSSA
8
D
OUT
47 VDDA
DATA REGISTER
48 VSSA
49 TXDATA
50 VRP
4
51 RXIP
VSS
52 RXIN
53 RXQP
54 RXQN
55 NC
I/O Function
O Key output terminal Not used (open)
I Selection input of the model Fixed at "L" in this set
I/O
Not used (open)
I
Selection input of the test mode Not used (open)
O
Serial data output to the liquid crystal display unit (LCD501)
I Key return signal input from the key matrix "L" input when key pressing
— Ground terminal (for core)
— Power supply terminal (+5V) (for core)
— Power supply terminal (+5V) (for pad)
— Ground terminal (for core)
I Sub system clock input terminal (32.768 kHz) Not used (open)
O Sub system clock output terminal (32.768 kHz) Not used (open)
O
Key send signal output to the key matrix
O
Key output terminal Not used (open)
I
Transmit data input from the CODEC (IC401)
O
Receive data output to the CODEC (IC401)
O Master clock signal output to the CODEC (IC401)
O Reset signal output to the CODEC (IC401) "L": reset
O Interface clock signal output to the CODEC (IC401)
— Power supply terminal (+5V) (for pad)
— Ground terminal (for pad)
O
Key send signal output to the key matrix
O
Frame output to the CODEC (IC401)
I
ART input from the base unit
O
ART output terminal Not used (open)
O
Key send signal output to the key matrix
O Not used (open)
— Power supply terminal (+5V) (for pad)
O Chip select signal output to the liquid crystal display unit (LCD501) "L" active
— Power supply terminal (+5V) (for core)
—
Ground terminal (for core)
I
Setting terminal for the test mode "L": test mode Normally: fixed at "H"
O
LNA gain selection signal output to the RF unit "H": low gain
O
RX system enable signal output to the RF unit "H": enable
— Power supply terminal (+5V) (for analog)
— Ground terminal (for analog)
— Power supply terminal (+5V) (for analog)
— Ground terminal (for analog)
O Transmit data output to the RF unit
O Analog reference voltage output terminal
I
Receive data (I positive) input from the RF unit
I
Receive data (I negative) input from the RF unit
I
Receive data (Q positive) input from the RF unit
I Receive data (Q negative) input from the RF unit
— Not used (open)
– 48 –