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5
AK5381VT (MAIN ASSY : IC3101)
QQ
3 7 63 1515 0
• 96kHz 24 bit ∆∑ ADC
Pin Arrangement (Top view)
AINR
AINL
CKS1
VCOM
AGND
VA
VD
DGNS
Pin Function
No.
Pin Name
1
AINR
2
AINL
3
CKS1
4
VCOM
5
AGND
TE
6
VA
L 13942296513
7
VD
8
DGND
9
SDTO
10
LRCK
11
MCLK
12
SCLK
13
PDN
14
DIF
15
CKS2
16
CKS0
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1
16
CKS0
2
15
CKS2
3
14
DIF
4
13
PDN
5
12
SCLK
6
11
MCLK
7
10
LRCK
8
9
SDTO
I/O
I
R ch analog input
I
L ch analog input
I
Mode select 1
O
Common voltage output, bias voltage of VA/2 and ADC input
−
Analog ground
−
Analog power supply, 4.5V to 5.5V
−
Digital power supply, 2.7 to 5.5V (fs = 4k to 48kHz), 3.0 to 5.5V (fs = 48k to 96kHz)
−
Digital ground
O
Audio serial data output, outputs "L" in the power down mode.
I/O
Channel clock I/O, outputs "L" by master mode in the power down mode.
I
Master clock input
I/O
Audio serial data clock, outputs "L" by master mode in the power down mode.
I
Power down mode
I
Audio interface format, "H" : 24 bit I2S compatibility, "L" : 24 bit MSB justify
I
Mode select 2
I
Mode select 0
x
ao
y
i
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8
Block Diagram
AINL
2
AINR
1
VCOM
4
Function
Q Q
3
6 7
1 3
"H": power up, "L": power down
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.
DVR-220-S
6
7
2 9
9 4
2 8
VA
AGND
VD
DGND
MCLK
6
5
7
8
Clock
Divider
∆∑
Decimation
Modulator
Filter
∆∑
Decimation
Modulator
Filter
Voltage
Serial I/O
Reference
Interface
15
3
16
13
CKS2
CKS1
CKS0
PDN
1 5
0 5
8
2 9
9 4
m
co
7
8
9 9
A
11
10
LRCK
12
SCLK
9
SDTO
B
14
DIF
C
2 8
9 9
D
E
F
101
8
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