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5. INPUT TERMINAL PIN ASSIGNMENT
5.1. Input Signal & Power (LVDS, Connector : DF19L-20P-1H : Hirose)
P
N I
N
O
S
Y
M
1
VDD
2
VDD
3
GND
4
GND
RxIN0-
5
RxIN0+
6
7
GND
RxIN1-
8
RxIN1+
9
10
GND
RxIN2-
11
RxIN2+
12
GND
13
RxCLK-
14
RXCLK+
15
16
GND
17
GND
GND
18
19
GND
20
GND
Panel Specification
B
O
L
POWER SUPPLY +3.3V
POWER SUPPLY +3.3V
GROUND
GROUND
LVDS Differential Data INPUT
LVDS Differential Data INPUT
GROUND
LVDS Differential Data INPUT
LVDS Differential Data INPUT
GROUND
LVDS Differential Data INPUT
LVDS Differential Data INPUT
GROUND
LVDS Differential Data INPUT
LVDS Differential Data INPUT
GROUND
GROUND
GROUND
GROUND
GROUND
FUNCTION
P
O
L
A
R
T I
Y
R
E
M
A
Negative
R0~R5,G0
Positive
Negative
G1~G5,
B0,B1
Positive
Negative
B2~B5,Vsync
Hsync, Enable
Positive
Negative
Clock
Positive
R
K
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