Board Revision Register - GE SBC330 3U VPX Hardware Reference Manual

6.3 Board Revision Register

Publication No. SBC330-0HH/3
This records the revision of the board, the FPGA and the CPLD release. This is
useful in identification and to system or FTS software, which may need to change
behavior according to any of these parameters. At present, PCB revisions are
recorded, although minor changes in FPGA or CPLD code may not be recorded.
The register is read‐only, hard‐coded and cannot be updated by any software.
The register is echoed in power up defaults loaded into the M8641 on the Local
AD bus lines. This replication is for ease of use with an emulator.
Chip Select CS2
Offset 0x000C
Reset value Depends on board revision
LAD Bit Reg Bit R/W
15 0 R
14 1 R
13 2 R
12 3 R
11 4 R
10 5 R
9 6 R
8 7 R
7 8 R
6 9 R
5 10 R
4 11 R
3 12 R
2 13 R
1 14 R
0 15 R
Description
PCB rev bit 0
PCB rev bit 1
PCB rev bit 2
PCB minor rev bit 0
PCB minor rev bit 1
FPGA rev bit 0
FPGA rev bit 1
FPGA rev bit 2
FPGA rev bit 3
FPGA rev bit 4
CPLD rev bit 0
CPLD rev bit 1
CPLD rev bit 2
Power Manager rev bit 0
Power Manager rev bit 1
Power Manager rev bit 2
FPGA Registers 51