Watchdog 0 And 1 Interrupt Registers; Axis Timestamp Registers - GE SBC330 3U VPX Hardware Reference Manual

6.17 AXIS Timestamp Registers

Publication No. SBC330-0HH/3

6.16.3 Watchdog 0 and 1 interrupt registers

Chip Select CS2
Offset 0x00A0 (Watchdog 0)
0x00A4 (Watchdog 1)
LAD Bit Reg Bit R/W
15 to 0 0 to 15 R/W
The AXIS timestamp timer is accessible to both cores as three 16‐bit registers to
make up a 48‐bit time. The timer does not start until the Axis Timer Control
Register is set up, so it does not run from power up, which saves power if it is not
used. The timer starts when it is released from reset via the Axis Timer Control
Register.
NOTE
As the timer is in the FPGA, it is a shared resource. Although both cores can see and read the timer,
they can never read it at exactly the same time, since each core's access would create a separate
transaction on the processor's local bus.
On boards that support it, the AXIS timer is associated with two dedicated pins
on one of the backplane connectors – AXIS_TIME_CLK and AXIS_RESET, which
facilitates precision data time‐stamping across an entire system. On SBC330, the
Axis Timer function, if used, takes over the GPIO lines 0 and 1 such that.
GPIO(0) = AXIS_TIME_CLOCK : connector P2 pin A:15
GPIO(1) = AXIS _TIME_RST : connector P2 pin B:15
The Axis Timer Control Register dictates whether the clock source for the Axis
timer is from the 66.6 MHz on‐board clock or whether it is from an external off‐
board clock. SBC330 has the ability to receive an external off‐board high speed
differential clock on the VPX‐specified REF_CLK_P, REF_CLK_N signals on P0.
Frequencies of up to 50 MHz can be handled.
In a system, there must therefore be an AXIS Timestamp Master, which drives the
clock and reset lines to the backplane, and one or more AXIS Timestamp
Receivers, which use the externally provided clock and reset signals from the
backplane. Writing to the Time Stamp Reset bit only has an effect when the
SBC330 is set up as AXIS Timestamp Master. A write of '0'‐'1'‐'0' to the Reset bit
toggles the Reset line on the backplane and synchronizes all timestamp counters
on all boards to 0x0000 0000 0000.
AXIS Timer Clock frequencies available on the SBC330 are 100/133 MHz (plus
66.6 MHz, 25 MHz, 8 MHz 250 KHz). The Prescaler, which is only active on the
AXIS Timestamp Master, divides the selected clock.
The AXIS time is updated only when the Least Significant Word (LSW) is read at
offset 0x002C, so the time must be read by reading the least significant word first.
Description
Watchdog interrupt value: 0 to 65535
Reset Value
0xFFFF
FPGA Registers 67