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5 Hardware Interface
5.4 Trigger
5.4.1 Trigger Modes
The following sections show the timing diagram for the trigger modes. The signal ExSync
denotes the trigger signal that is provided either by the interface trigger or the I/O trigger (see
Section 4.6). The other signals are explained in Table 5.4. For an active high trigger signal, the
image acquisition begins with the rising edge of the trigger signal. The image is read out after
the pre-configured exposure time. After the readout, the sensor returns to the reset state and
the camera waits for a new trigger pulse (see Fig. 5.7).
The data is output on the rising edge of the pixel clock, the handshaking signals FRAME_VALID
(FVAL) and LINE_VALID (LVAL) mask valid image information. The signal SHUTTER in Fig. 5.7
indicates the active integration phase of the sensor and is shown for clarity only.
P C L K
E X S Y N C
S H U T T E R
F V A L
L V A L
D V A L
D A T A
Figure 5.7: Trigger timing diagram for camera controlled exposure
5.4.2 Trigger Delay
The total delay between the trigger edge and the camera exposure consists of the delay in the
frame grabber and the camera (Fig. 5.8). Usually, the delay in the frame grabber is relatively
large to avoid accidental triggers caused by voltage spikes (see Fig. 5.9).
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