HP 3320A Operating And Service Manual page 28

Model 3320A/B
and H DAC, which are HIGH true. Table 1-2 lists the signal
levels required.
NOTE
In the 3320B the Data Input/Output bit 8
(DI08) and Service Request (SRQ) are not used
(no connections).
4·30. GPIB Basic Theory and Operation. The 3320B GPIB
circuits employ both combinational and sequential logic to
convert the ASClI data input into parallel BCD data for
controlling the various settings of frequency and amplitude.
A black diagram of the GPIB circuits is shown in Figure
4-9.
4-31. By means of the GPIB control lines, each appropriate
ASCII character on the data lines is accepted by the Input
Circuit. As each data character is accepted, a Data Accepted
Signal (H DAC) is supplied back
to
the remote controller to
indicate that the data has been accepted. After a data
character has been processed, RFD is allowed to go HIGH,
indicating to the remote controller that the 33208 is ready
for new data.
4·32. To provide isolation, each ASCII character and
various control data is transferred to the controller block
by
means of pulse transformers or photo-couplers. The
controller decodes the ASCII character into a "Preface
Command" or "Numerical Data". For example, if the
ASC II characters A, I, 2, 3 and 4 were accepted by the
Input Circuit in sequence, the first character A would be
decoded in the controller and applied to the Latches
(storage registers) as an Amplitude Preface Command. The
next four ASCII characters, being numerals. would be
decoded as numerical data and applied to the Latches
prefaced by the earlier Amplitude Preface Command.
4-33. The Latches and associated circuits function primar-
ily as a series to parallel converter.
It
converts the preface
commands and the serial numerical data from the controller
into stored parallel BCD data.
4-34. The main function of the BCD Circuits is to process
the BCD format used for controlling the frequency and
amplitude sections.
4-35. The BCD data for the frequency setting is converted
to 9's complement and applied directly to the frequency
section of the 3320B. The 9's complement of a number is a
Section IV
number which, when added to the first number, equals
nine. For example, the 9's complement of a BCD 2 is a
BCD 7 since 2 + 7
=
9. The BCD data for the amplitude
settings is added to a preset BCD number in the BCD
Circuits. This BCD addition provides the proper BCD
numbers for controlling the amplitude reference and 10
dBI
step attenuator in the amplitude section of the 3320B.
Since the 3320B output is calibrated in dBm, the magni-
tude of the preset BCD number depends on the output
impedance of the 3320B.
4-36. In addition to processing the amplitude and fre-
quency data, the BCD circuit also processes the remaining
programmable parameters such as vernier frequency, lev-
eling and delay. The delay flag shown in Figure 4-9 holds
the GPIB RFD LOW for the amount of delay time
programmed.
NOTE
A more detailed functional block diagram of all
the assemblies IA37, A 38, A25, A23 and
A24B) used in the GPIB controller
is
shown in
Figure 7·5.
4·37. Reset Conditions. When power is first appUed to the
3320B, Reset and Clear signals from the controller block
reset the latches to the turn on conditions given in Section
III. However, the Resel signal also clears the Remote
Flip-Flop, forcing the 3320B into local (front panel)
control. LocaJ control is automatic when power is initially
applied even if the RE is held LOW.
4·3B. Addressing the 33208. When the MRE is LOW, the
lnput Circuit waits for the DAV
10
go LOW indicating that
the data information is valid. When L DAV !s received, the
information on the dala lines, LOla
1
through LDI07, are
compared
to
the 3320B address. If they match, the 3320B
is addressed and the DAC signal is allowed to go HIGH to
indicate that the address has been accepted.
NOTE
When power
is
initially applied the 3320B may
or may not be addressed. This
is
why the
"Address Clear" command (ASCII
1) is
recom-
mended prior to addressing any inslrumetll(s)
on the GPIB Bus.
4-39. Remote Programming. After the 3320B has been
BCD LINES
FROM FRONT PANEL
TO
CONTROLLER
I--
LATCHES
BCD
BCD
AMPLITUDE
AND
J
CIRCUITS
FREQUENCY
GPiB
A38 f---- A25
A23 ANOA24E1
SECTIONS
DATA L1NES---'
I N PUT
GPIB , ___
A37
DELAY FLAG
CONTROL LINES
~
:n~O"'/a-8-'508
Figure 4-9. GPIB Controller.
4-5