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NOTE 1: LDgic signal levels are shown by the letters H or L
preceding the name of the line. The Hand L indicates the true state
(signal present). Voltage levels for the Hand L are:
H
=
+5V
L
=
OV
Example:
H Delay Flag - indicates the delay flag line should be
+
5 V
when a delay flag signal is present.
L Data Valid - indicates the data valid line should be 0 V when
a data valid signal is present.
NOTE 2: LDcation of jumpers on A37 Assembly indicates GPIB
Address of instrument. Instruments are shipped from factory with
Address 63, jumpered in as shown on schematic. To change Address,
move jumpers to desired number according to the following table:
BIT
WEIGHT
b1
1
b2
2
b3
4
b4
10
b5
20
Note: b6 (40 weight) is "hard-wired".
b7 (80 weight) is "hard-wired".
NOTE 3: Instruments are shipped from factory with jumper A-B on
A37 Assembly connected. The jumper wire can be removed and a
ground connected to B to inhibit remote enable.
If it is desired to control local or remote mode of the instrument
with a switch, connect the switch to the S.W. REMOTE ENABLE
point on the A39 Assembly. Grounding the S.W. REMOTE
ENABLE point forces local mode. No connection (switch open) to
the S.W. REMOTE ENABLE point will allow the instrument to be
remotely programmed, as outlined in Section III, if jumper A-B is
connected.
NOTE 4: Instruments are shipped from factory with jumper A-B on
A38 Assembly removed (disconnected). With the jumper discon-
nected, the last remote program for amplitude, frequency, etc., is
retained when changing from remote to local and then back to
remote. If it is not desired to retain the last remote program,
connect a jumper between points A and B. This will enabte the Data
Selector/Storage Registers on the A25 Assembly to be reset by the
Local Enable Command to the initial remote turn-on condition
listed below.
Frequency
800 Hz
Range
1000 Hz
Amplitude
-69.00 dBm
Vernier
out/O Hz
Delay
1500 ms
Leveling ........................• ON (>10 Hz)
7-28
NOTE 5: The Logic diagram for a 4 Line to 10 Line Decoder is
shown below. IC12, 13, 14 along with NOR gates IC6, 7,11 and
Inverter
IC15 constitute a "data bit decoder". See Figure 7-5 for r
truth table.
INPUT
DECIMAL OUTPUT
12
13
14
15
1
2
3
4
5
6
7
9
10
11
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
L
H
H
H
H
H
H
H
L
L
H
H
H
H
H
L
fi
H
H
H
H
H
L
H
L
L
H
H
H
H
L
H
H
H
H
H
L
H
L
H
H
H
H
H
H
L
H
H
H
H
L
H
H
L
H
H
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
NOTE 6: Logic diagram of IC is shown below.
POSITIvE
lOGIC
' 1 ' 1
'n
+1
J
K
Q
o
0
On
o
I
0
I
I
I
I
an
NOTES:
Un • BIT TIME BEFORE
CLOCK PULSE
2.11'1
+-,=
BIT TIME AFTER
CLOCK PULSE
3.
a-an
MEANS OUTPUTS DO NOT CHANGE
STATES WITH CLOCK PULSE
4.0·O n MEANS OUTPUTS CHANGE STATES
WITH CLOCK PULSE
Low i.,ut to Clo., .ot.
Q
to 10,leel O.
Cloor I. In_pon4lont of Cloc:k.
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