Advanced Chipset Features - Abit IP35V User Manual

2.4 Advanced Chipset Features

DRAM Timing Selectable
x - CAS Latency Time
x - RAS# to CAS# Dealay
x - RAS# Precharge
x - Precharge Delay
x - Refresh Cycle Time
x - Write Recovery Time
x - Write to Read Delay
x - Act to Act Time
x - Read to Precharge
x - Command Rate
► PCIe Root Port Function
Init Display First
PEG Force X1
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5: Previous Values
DRAM Timing Selectable
This item sets the optimal timings for the following four items, depending on the memory
module you are using. The default setting "By SPD" configures these four items by reading the
contents in the SPD (Serial Presence Detect) device. The EEPROM on the memory module
stores critical parameter information about the module, such as memory type, size, speed,
voltage interface, and module banks. The following items will be available to make adjustments
by selecting option [Manual].
- CAS Latency Time
- RAS# to CAS# Dealay (tRCD)
- RAS# Precharge
- Precharge Delay
- Refresh Cycle Time
- Write Recovery Time
- Write to Read Delay
- Act to Act Time
- Read to Precharge
- Command Rate
IP35V
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
By SPD
(tCL) Auto
(tRCD) Auto
(tRP) Auto
(tRAS) Auto
(tRFC) Auto
(tWR) Auto
(tWTR) Auto
(tRRD) Auto
(tRTP) Auto
Auto
Press Enter
PCI Slot
Disabled
F6: Fail-Safe Defaults
(tCL)
(tRP)
(tRAS)
(tRFC)
(tWR)
(tWTR)
(tRRD)
(tRTP)
Item Help
F7: Optimized Defaults
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