Lantronix DSTni DSTni-EX User Manual
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Lantronix DSTni DSTni-EX User Manual

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DSTni-EX User Guide
Section Five
Part Number 900-335
Revision A 3/04

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Summary of Contents for Lantronix DSTni DSTni-EX

  • Page 1 DSTni-EX User Guide Section Five Part Number 900-335 Revision A 3/04...

  • Page 3: Copyright And Trademark

    © 2003 Lantronix, Inc. All rights reserved. Lantronix and the Lantronix logo, and combinations thereof are registered trademarks of Lantronix, Inc. DSTni is a registered trademark of Lantronix, Inc. Ethernet is a registered trademark of Xerox Corporation. All other product names, company names, logos or other designations mentioned herein are trademarks of their respective owners.

  • Page 4: Warranty

    Lantronix, freight prepaid. Upon verification of warranty, Lantronix will -- at its option -- repair or replace the product and return it to the customer freight prepaid. If the product is not under warranty, the customer may have Lantronix repair the unit on a fee basis or return it.

  • Page 5: Table Of Contents

    Contents Copyright & Trademark ________________________________________________________i Warranty___________________________________________________________________ ii Contents___________________________________________________________________ iii List of Tables _______________________________________________________________ iv List of Figures_______________________________________________________________ vi 1: About This User Guide _________________________________________ 1 Intended Audience ___________________________________________________________ 2 Conventions ________________________________________________________________ 2 Navigating Online____________________________________________________________ 2 Organization________________________________________________________________ 3 2: SPI Controller ________________________________________________ 4 Theory of Operation __________________________________________________________ 4 SPI Background___________________________________________________________ 4 DSTni SPI Controller _______________________________________________________ 4...

  • Page 6: List Of Tables

    Host Mode Operation ________________________________________________________ 50 Sample Host Mode Operations ________________________________________________ 51 USB Pull-up/Pull-down Resistors_______________________________________________ 53 USB Interface Signals _______________________________________________________ 54 5: CAN Controllers _____________________________________________ 55 CANBUS Background _______________________________________________________ 56 Data Exchanges and Communication _________________________________________ 56 Arbitration and Error Checking ______________________________________________ 56 CANBUS Speed and Length ________________________________________________ 57 Features __________________________________________________________________ 57 Theory of Operation _________________________________________________________ 58...
  • Page 7 Table 3-17. Clock Control Register ... 28 Table 3-18. Clock Control Register Definitions... 28 Table 3-19. Extended Slave Address Register ... 29 Table 3-20. Extended Slave Address Register Definitions... 29 Table 3-21. Software Reset Register ... 29 Table 3-22. Software Reset Register Definitions... 29 Table 4-1.
  • Page 8 Table 5-34. Tx/Rx Message Level Register ... 71 Table 5-35. Tx/Rx Message Level Register Definitions... 71 Table 5-36. Interrupt Flags ... 72 Table 5-37. Interrupt Flag Definitions ... 72 Table 5-38. Interrupt Enable Registers ... 73 Table 5-39. Interrupt Enable Register Definitions... 73 Table 5-40.

  • Page 9: 1: About This User Guide

    This User Guide describes the technical features and programming interfaces of the Lantronix DSTni-EX chip (hereafter referred to as “DSTni”). DSTni is an Application Specific Integrated Circuit (ASIC)-based single-chip solution (SCS) that integrates the leading-edge functionalities needed to develop low-cost, high-performance device server products.

  • Page 10: Intended Audience

    Intended Audience This User Guide is intended for use by hardware and software engineers, programmers, and designers who understand the basic operating principles of microprocessors and their systems and are considering designing systems that utilize DSTni. Conventions This User Guide uses the following conventions to alert you to information of special interest. The symbols # and n are used throughout this Guide to denote active LOW signals.

  • Page 11: Organization

    Organization This User Guide contains information essential for system architects and design engineers. The information in this User Guide is organized into the following chapters and appendixes. Section 1: Introduction Describes the DSTni architecture, design benefits, theory of operations, ball assignments, packaging, and electrical specifications.

  • Page 12: 2: Spi Controller

    This chapter describes the DSTni Serial Peripheral Interface (SPI) controller. Topics include: Theory of Operation on page 4 SPI Controller Register Summary on page 5 SPI Controller Register Definitions on page 6 Theory of Operation SPI Background SPI is a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed length (one to eight bits) to be shifted into and out of the device at a programmable bit-transfer rate.

  • Page 13: Spi Controller Register Summary

    When operating as a slave, the SPI clock signal (SCLK) must be slower than 1/8th of the CPU clock (1/16th is recommended). Note: The SPI is fully synchronous to the CLK signal. As a result, SCLK is sampled and then operated on.

  • Page 14: Spi Controller Register Definitions

    SPI Controller Register Definitions SPI_DATA Register SPI_DATA is the SPI Controller Data register. OFFSET FIELD RESET Bits Field Name 15:8 DATA[7:0] Table 2-2. SPI_DATA Register B800 Table 2-3. SPI_DATA Register Definitions Description Reserved Always returns zero. Data The location where the CPU reads data from or writes data for the SPI interface. DATA[7:0]...

  • Page 15: Ctl Register

    CTL Register CTL is the SPI Controller Control register. OFFSET FIELD RESET Bits Field Name 15:8 IRQENB AUTODRV INVCS PHASE CKPOL MSTN Table 2-4. CTL Register B802 Table 2-5. CTL Register Definitions Description Reserved Always returns zero. Interrupt Request Enable 1 = enable the SPI to generate interrupts.

  • Page 16: Spi_Stat Register

    SPI_STAT Register To clear a bit in the SPI_STAT register, write a 1 to that bit. OFFSET FIELD RESET Bits Field Name 15:8 OVERRUN TXRUN SLVSEL Table 2-6. SPI_STAT Register B804 Table 2-7. SPI_STAT Register Definitions Description Reserved Always returns zero. Interrupt Request 1 = indicates the end of a master mode transfer, or that SLVSEL_N input has gone HIGH on a slave transfer.

  • Page 17: Spi_Ssel Register

    SPI_SSEL Register SPI_SSEL is the Slave Select Bit Count register. OFFSET FIELD RESET Bits Field Name 15:8 BCNT[2:0] SELECTO Bit [2] Table 2-8. SPI_SSEL Register B806 BCNT[2:0] Table 2-9. SPI_SSEL Register Definitions Description Reserved Always returns zero. Bit Shift Count Controls the number of bits shifted between the master and slave device during a transfer, when this device is the master.

  • Page 18: Dvd_Cntr_Lo Register

    DVD_CNTR_LO Register DVD_CNTR_LO is the DVD Counter Low Byte register. OFFSET FIELD RESET Table 2-12. DVD_CNTR_LO Register Definitions Bits Field Name 15:8 DVDCNT[7:0] DVD_CNTR_HI DVD_CNTR_HI is the DVD Counter High Byte register. OFFSET FIELD RESET Table 2-14. DVD_CNTR_HI Register Definitions Bits Field Name 15:8...

  • Page 19: C Controller

    This chapter describes the DSTni I Features on page 11 Block Diagram on page 12 Theory of Operation on page 12 Programmer’s Reference on page 22 C Controller Register Summary on page 22 C Controller Register Definitions on page 23 Features Master or slave operation Multmaster operation...

  • Page 20: Block Diagram

    Block Diagram Figure 3-1 shows a block diagram of the DSTni I Figure 3-1. DSTni I Theory of Operation C Background The I C bus is a popular serial, two-wire interface used in many systems because of its low overhead. Capable of 100 KHz operation, each device connected to the bus is software addressable by a unique address, with a simple master/slave protocol.

  • Page 21: I 2 C Controller

    C Controller The I C controller base address is D000h and shares INT2 with the SPI controller. The I interface requires two bi-directional buffers with open collector (or open drain) outputs and Schmitt inputs. Operating Modes The following sections describe the possible I Master Transmit Mode, page 13 Master Receive Mode, page 16 Slave Transmit Mode, page 19...

  • Page 22: Table 3-1. Master Transmit Status Codes

    Table 3-1. Master Transmit Status Codes Code C State Addr + W transmitted, ACK received Addr + W transmitted, ACK not received Arbitration lost Arbitration lost, SLA + W received, ACK transmitted Arbitration lost, general call addr received, ACK transmitted Arbitration lost, SLA + R received, ACK transmitted...

  • Page 23: Table 3-2. Codes After Servicing Interrupts (Master Transmit)

    Servicing the Interrupt After servicing this interrupt, and transmitting the second part of the address, the Status register contains one of the codes in Table 3-2. Note: If a repeated START condition transmits, the status code is 10h instead of 08h. Table 3-2.

  • Page 24: Table 3-3. Status Codes After Each Data Byte Transmits

    Transmitting Each Data Byte After each data byte transmits, the IFLG is set, and one of the three status codes in Table 3-3 is in the Status register. Table 3-3. Status Codes After Each Data Byte Transmits Code C State Data byte transmitted, ACK received Data byte transmitted,...

  • Page 25: Table 3-4. Master Receive Status Codes

    Table 3-4. Master Receive Status Codes Code C State Addr + W transmitted, ACK received Addr + W transmitted, ACK not received Arbitration lost Arbitration lost, SLA + W received, ACK transmitted Arbitration lost, general call addr received, ACK transmitted Arbitration lost, SLA + R received, ACK transmitted...

  • Page 26: Table 3-5. Codes After Servicing Interrupt (Master Receive)

    Servicing the Interrupt After servicing this interrupt and transmitting the second part of the address, the Status register contains one of the codes in Table 3-5. Table 3-5. Codes After Servicing Interrupt (Master Receive) Code C State Arbitration lost Arbitration lost, SLA + W received, ACK transmitted Arbitration lost,...

  • Page 27: Table 3-6. Codes After Receiving Each Data Byte

    Receiving Each Data Byte After receiving each data byte, the IFLG is set and one of three status codes in Table 3-6 is in the Status register. When all bytes are received, set the STP bit by writing a 1 to it in the Control register. The I controller: Transmits a STOP condition Clears the STP bit...
  • Page 28 − The IFLG is set and the Status register contains B8h. − After the last transmission byte loads in the Data register, clear AAK when IFLG clears. − After the last byte is transmitted, the IFLG is set and the Status register contains C8h.

  • Page 29: Bus Clock Considerations

    Bus Clock Considerations Bus Clock Speed The I C bus can be defined for bus clock speeds up to 100 Kb/s and up to 400 Kb/s in fast mode. To detect START and STOP conditions on the bus, the M I 10 times faster than the fastest master bus clock on the bus.

  • Page 30: Programmer's Reference

    Resetting the I There are two ways to reset the I Using the RSTIN# pin Writing to the Software Reset register Using the RSTIN# pin reset method: Clears the Address, Extended Slave Address, Data, and Control registers to 00h. Sets the Status register to F8h. Sets the Clock Control register to 00h.

  • Page 31: I 2 C Controller Register Definitions

    C Controller Register Definitions Slave Address Register OFFSET EXTENDED ADDRESS FIELD SLA6 RESET Bits Field Name SLA6 – SLA0 Table 3-8. Slave Address Register D000 SLA5 SLA4 SLA3 SLA2 Table 3-9. Address Register Definitions Description Slave Address For 7-bit addressing, these bits are the 7-bit address of the I mode.

  • Page 32: Data Register

    Data Register The Data register contains the transmission data/slave address or the receipt data byte. In transmit mode, the byte is sent most-significant bits first. In receive mode, the first bit received is placed in the register’s most-significant bits. After each byte transmits, the Data register contains the byte present on the bus; therefore, if arbitration is lost, the Data register has the correct receive byte.

  • Page 33: Control Register

    Control Register OFFSET FIELD ENAB RESET Table 3-13. Control Register Definitions Bits Field Name Description Extended Slave Address l = interrupt line (INTR) goes HIGH when the IFLG bit is set. 0 = interrupt line remains LOW (default). ENAB Extended Slave Address 1 = I address if the GCE bit in the ADDR register is set.

  • Page 34: Status Register

    Bits Field Name Description Acknowledge 1 = send Acknowledge (LOW level on SDA) during acknowledge clock pulse on the I − The general call address is received and the GCE bit in the ADDR register is − A data byte is received in master or slave mode. 0 in slave transmitter mode = send Not Acknowledge (HIGH level on SDA) when a data byte is received in master or slave mode.

  • Page 35: Table 3-15. Status Register Definitions

    Table 3-15. Status Register Definitions Bits Field Name Description STATUS CODE Status Code Five-bit status code. See Table 3-16. Reserved Code Description Bus error START condition sent Repeated START condition sent Address + write bit sent, ACK received Address + write bit sent ACK not received Data byte sent in master mode, ACK received Data byte sent in master mode, ACK not received Arbitration lost in address or data byte...

  • Page 36: Clock Control Register

    Clock Control Register The Clock Control register is a Write Only register that contains seven least-significant bits. These least-significant bits control the frequency: At which the I Of the I C clock line (SCL) when the I The CPU clock frequency (of CLK) is first divided by a factor of 2 by bits 2 –...

  • Page 37: Extended Slave Address Register

    Extended Slave Address Register Table 3-19. Extended Slave Address Register OFFSET FIELD SLAX7 SLAX6 RESET Table 3-20. Extended Slave Address Register Definitions Bits Field Name SLAX7 SLAX6 SLAX5 SLAX4 SLAX3 SLAX2 SLAX1 SLAX0 Software Reset Register OFFSET FIELD HRST RESET Table 3-22.

  • Page 38: 4: Usb Controller

    This chapter describes the DSTni Universal Serial Bus (USB) controller. Topics include: Features on page 30 Theory of Operation on page 31 USB Register Summary on page 38 USB Register Definitions on page 39 Host Mode Operation on page 50 Sample Host Mode Operations on page 51 USB Pull-up/Pull-down Resistors on page 53 USB Interface Signals on page 54...

  • Page 39: Theory Of Operation

    Theory of Operation USB Background USB is a serial bus operating at 12 Mb/s. USB provides an expandable, hot-pluggable Plug- and-Play serial interface that ensures a standard, low-cost socket for adding external peripheral devices. USB allows the connection of up to 127 devices. Devices suitable for USB range from simple input devices such as keyboards, mice, and joysticks, to advanced devices such as printers, scanners, storage devices, modems, and video-conferencing cameras.

  • Page 40: Usb Hardware/Software Interface

    Microprocessor Interface The USB microprocessor interface is made up of a slave interface and a master interface. The slave interface consists of a number of USB control and configuration registers. USB internal registers can be accessed using a simple microprocessor interface. The master interface is the integrated DMA controller that transfers packet data to and from memory.

  • Page 41: Figure 4-1. Buffer Descriptor Table

    Figure 4-1. Buffer Descriptor Table The microprocessor manages buffers intelligently for the USB by updating the BDT as necessary. This allows the USB to handle data transmission and reception efficiently while the microprocessor performs communication-overhead processing and other function-dependent applications. Because the microprocessor and the USB share buffers, DSTni uses a simple semaphore mechanism to distinguish who is allowed to update the BDT and buffers in system memory.

  • Page 42: Table 4-1. Usb Data Direction

    Device Host Addressing BDT Entries Before describing how to access endpoint data via the USB or microprocessor, it is important to understand the BDT addressing mechanism. The BDT occupies up to 256 bytes of system memory. Sixteen bidirectional endpoints can be supported with a full BDT of 256 bytes. Eight bytes are needed for each USB endpoint direction.

  • Page 43: Table 4-4. Bdt Data Used By Usb Controller And Microprocessor

    Table 4-4. BDT Data Used by USB Controller and Microprocessor USB Controller Determines… Who owns the buffer in system memory Data0 or Data1 PID Release Own upon packet completion No address increment (FIFO Mode) Data Toggle Synchronization enable Amount of data to be transmitted or received Where the buffer resides in system memory Table 4-5 shows the USB BD format.

  • Page 44: Table 4-6. Usb Buffer Descriptor Format Definitions

    Table 4-6. USB Buffer Descriptor Format Definitions Bits Field Name Description BD Owner Specifies which unit has exclusive access to the BD. 0 = microprocessor has exclusive and entire BD access; USB ignores all other fields in the BD 1 = USB has exclusive BD access SIE writes a 0 to this bit when it completes a token, except when KEEP=1.

  • Page 45: Usb Transaction

    USB Transaction When the USB transmits or receives data: 1. The USB uses the address generation in Table 4-5 to compute the BDT address. 2. After reading the BDT, if the OWN bit equals 1, the SIE DMAs the data to or from the buffer indicated by the BD’s ADDR field.

  • Page 46: Usb Register Summary

    USB Register Summary Mnemonic Offset INT_STAT ERR_STAT STAT ADDR FRM_NUM TOKEN ENDPT1 ENDPT2 ENDPT3 ENDPT4 ENDPT5 ENDPT6 ENDPT7 Table 4-7. USB Register Summary Register Description Bits for each interrupt source in the USB. Bits for each error source in the USB. Transaction status in the USB.

  • Page 47: Usb Register Definitions

    USB Register Definitions The following sections provide the USB register definitions. In these sections: The register mnemonic is provided for reference purposes. The register address shown is the address location of the register in the CRB. The initialization value shown is the register’s initialization value at reset. Interrupt Status Register The Interrupt Status register contains bits for each of the interrupt sources in the USB.
  • Page 48 Bits Field Name Description USB_RST Enable/Disable USB_RST Interrupt 1 = enable the USB_RST interrupt. 0 = disable the USB_RST interrupt (default). STALL Stall Used in target and host modes. • In target mode, it asserts when the SIE sends a stall handshake. •...

  • Page 49: Error Register

    Error Register The Error register contains bits for each of the error sources in the USB. Each of these bits is qualified with its respective error enable bits. The result is OR’ed together and sent to the ERROR bit of the Interrupt Status register. Once an interrupt bit has been set it may only be cleared by writing a one to the respective interrupt bit.
  • Page 50 Bits Field Name Description DMAERR 1 = USB requests a DMA access to read a new BDT, but is not given the bus before USB needs to receive or transmit data. • If processing a TX transfer, this causes a transmit data underflow condition. •...

  • Page 51: Status Register

    Status Register The Status register reports the transaction status within the USB. When the microprocessor has received a TOK_DNE interrupt, the Status register should be read to determine the status of the previous endpoint communication. The data in the status register is valid when the TOK_DNE interrupt bit is asserted.
  • Page 52 Bits Field Name Description RESET USB Reset Signal 1 = enables the USB to generate USB reset signaling. This allows the USB to reset USB peripherals. This control signal is only valid in host mode, (i.e., HOST_MDOE_EN=1). Software must set RESET to 1 for the required amount of time and then clear it to 0 to end reset signaling.

  • Page 53: Address Register

    Address Register The Address register contains the unique USB address that the USB decodes in peripheral mode (HOST_MODE_EN=0). In host mode (HOST_MODE_EN=1), the USB transmits this address with a TOKEN packet. This enables the USB to uniquely address any USB peripheral. In either mode the USB_EN bit in the Control register must be set.

  • Page 54: Frame Number Registers

    Frame Number Registers The Frame Number registers contain the 11-bit frame number. The current frame number is updated in these registers when a SOF_TOKEN is received. OFFSET FIELD RESET Table 4-17. Frame Number Register Definitions Bits Field Name 15:11 10:0 FRM[10:0] Table 4-16.

  • Page 55: Token Register

    Token Register The Token register performs USB transactions when in host mode (HOST_MODE_EN=1). When the host microprocessor wants to execute a USB transaction to a peripheral, it writes the TOKEN type and endpoint to this register. After this register is written, the USB begins the specified USB transaction to the address contained in the Address register.

  • Page 56: Table 4-18. Token Register

    OFFSET SOF Threshold Register FIELD CNT[7:0] RESET Bits Field Name 15:8 CNT[7:0] TOKEN_PID TOKEN_ENDPT Token_PID 0001 1001 1101 Table 4-18. Token Register TOKEN_PID Table 4-19. Token Register Definitions Description SOF Count Threshold Represent the SOF count threshold, in byte times. Token Type The token type that the SUB executes (see Table 4-20).

  • Page 57: Endpoint Control Registers

    Endpoint Control Registers The Endpoint Control registers contain the endpoint control bits for the 16 endpoints available on USB for a decoded address. These four bits define all the control necessary for any one endpoint. Endpoint 0 (ENDPT0) is associated with control pipe 0, which is required by USB for all functions.

  • Page 58: Host Mode Operation

    Table 4-23. Endpoint Control Register Definitions EP_CTL_DIS EP_RX_EN Host Mode Operation A unique feature of the USB core is its host mode logic. This logic lets devices such as digital cameras and palmtop computers work as a USB host controller. Host mode lets a peripheral such as a digital camera connect directly to a USB-compliant printer.

  • Page 59: Sample Host Mode Operations

    Sample Host Mode Operations Figure 3. Enable Host Mode and Configure a Target Device...

  • Page 60: Figure 4. Full-Speed Bulk Data Transfers To A Target Device

    Figure 4. Full-Speed Bulk Data Transfers to a Target Device...

  • Page 61: Usb Pull-Up/Pull-Down Resistors

    USB Pull-up/Pull-down Resistors USB uses pull-up or pull-down resistors to determine when an attach or detach event occurs on the bus. Host mode complicates the resistors, since it requires devices to operate as either a USB target device or a USB host. Figure 4-5 shows the two resistor combinations required for USB targets and hosts.

  • Page 62: Usb Interface Signals

    USB Interface Signals The clock input is required to be connected to a 12 MHz signal that is derived Clock (CLK) from the USB signals. The USB speed indicator is used by external USB transceiver logic to USP Speed determine which speed interface the USB is implementing. (SPEED) 1 = USB is operating at full speed.

  • Page 63: 5: Can Controllers

    This chapter describes the DSTni CAN controller. Topics include: CANBUS Background on page 56 Features on page 57 Theory of Operation on page 58 CAN Register Summaries on page 58 CAN Register Definitions on page 63 CAN Bus Interface on page 84 This chapter assumes you have a working knowledge of the CAN bus protocols.

  • Page 64: Canbus Background

    CANBUS Background CAN is a fast and highly reliable, multicast/multimaster, prioritized serial communications protocol that is designed to provide reliable and cost-effective links. CAN uses a twisted-pair cable to communicate at speeds of up to 1 MB/s with up to 127 nodes. It was originally developed to simplify wiring in automobiles.

  • Page 65: Canbus Speed And Length

    CANBUS Speed and Length Table 7-1 shows the relationship between the bit rate and cable length. Table 5-1. Bit Rates for Different Cable Lengths Features Three programmable acceptance filters − − Transmit Path − − Receive FIFO − − Bus coupler −...

  • Page 66: Theory Of Operation

    Theory of Operation The CAN controller appears to the microprocessor as an I/O device. Each peripheral has 256 bytes of I/O address space allocated to it. CAN0 and CAN1 share Interrupt 6. CAN Controller CAN0 CAN1 CAN Register Summaries DSTni contains two independent CAN channels. Operation and access to each device, however, is the same.
  • Page 67 Hex Offset Register RxMessage: ID, ID28-13 ID12-00 RxMessage: Data, D55-48, D63-56 D39-32, D47-40 D23-16, D31-24 D07-00, D15-08 RxMessage: RTR, IDE, DLC_3-0,AFI_2-0 RxMessage: Control Flags, Fifo_Lvl_2-0, MsgAval Transmitter and Receive Error Counter Error Status Message Level Threshold Interrupts Flags Interrupt Enable Register CAN mode, Loop_Back, Passive, Run CAN Bit Rate Div., cfg_bitrate_10-0 CAN tsegs...

  • Page 68: Detailed Can Register Map

    Detailed CAN Register Map Register Offset 0x00 TX Msg 0 0x02 0x04 0x06 0x08 0x0a 0x0c 0x0e TX Msg 0 Ctrl Flags 0x10 TX Msg 1 0x12 0x14 0x16 0x18 0x1a 0x1c 0x1e TX Msg 1 Ctrl Flags 0x20 TX Msg 2 0x22 0x24 0x26...
  • Page 69 Register Offset 0x30 RX Msg 0x32 0x34 0x36 0x38 0x3a 0x3c 0x3e RX Msg Flags 0x40 TX & RX Error Cnt 0x42 Error Status 0x44 TX/ RX Msglevel 0x46 IRQ flags 0x48 Enb. Reg. 0x4a Mode 0x4c Rate Divisor 0x4e tsegs 0x50 Acceptance...
  • Page 70 Register Offset 0x52 Acceptance Mask Register 0 0x54 0x56 0x58 Acceptance Code Register 0 0x5a 0x5c 0x5e Acceptance Mask Register 1 0x60 0x62 0x64 Acceptance Code Register 1 0x66 0x68 0x6a Acceptance Mask Register 2 0x6c 0x6e 0x70 Acceptance Code Register 2 0x72 0x74...

  • Page 71: Can Register Definitions

    CAN Register Definitions TX Message Registers To avoid priority inversion issues in the transmit path, three transmit buffers are available with a built-in priority arbiter. When a message is transmitted, the priority arbiter evaluates all pending messages and selects the one with the highest priority. The message priority is re-evaluated after each message abort event such as arbitration loss.

  • Page 72: Tx Message Registers

    Tx Message Registers Table 5-5 shows TxMessage_0 registers. The registers for TxMessage_1 and TxMessage_2 are identical except for the offsets. OFFSET ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 FIELD OFFSET ID12 ID11 ID10 ID09 ID08 ID07 ID06 ID05 ID04 ID03 ID02 ID01 ID00 FIELD OFFSET FIELD...

  • Page 73: Table 5-12. Txmessage_0:Ctrl Flags

    OFFSET FIELD Table 5-13. TxMessage_0 Register Definitions Field Name Description ID_28:ID_0 Message Identifier for Both Standard and Extended Messages Standard messages use ID_28 .. ID_18 D_63:D_0 Message Data Byte 1 is D_63, D_56; Byte 2 is D_55, D_48; and so on. Remote Bit Extended Identifier Bit DLC_3:DLC_0...

  • Page 74: Rx Message Registers

    RX Message Registers A 4-message-deep FIFO stores the incoming messages. Status flags indicate how many messages are stored. Additional flags determine from which acceptance filter the actual message is coming from. Figure 5-2. RX Message Routing uP Bus To read received messages: Wait for rx_msg interrupt.

  • Page 75: Rx Message Registers

    Rx Message Registers The following table shows RxMessage registers. See the complete register table at the start of this section. OFFSET ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 FIELD RESET Table 5-15. Rx Message: ID28 Register Definitions Bits Field Name 15:0...

  • Page 76: Table 5-20. Rx Message: Data 39

    OFFSET FIELD RESET Table 5-21. Rx Message: Data 39 Register Definitions Bits Field Name 15:0 D[39:40] OFFSET FIELD RESET Table 5-23. Rx Message: Data 23 Register Definitions Bits Field Name 15:0 D[23:24] OFFSET FIELD RESET Table 5-25. Rx Message: Data 7 Register Definitions Bits Field Name 15:0...

  • Page 77: Table 5-26. Rxmessage: Rtr

    OFFSET FIELD RESET R/W R/W R/W R/W R/W Table 5-27. Rx Message: RTR Register Definitions Bits Field Name 15:11 10:8 AFI[2:0] DLC[3:0] OFFSET FIELD RESET R/W R/W R/W R/W R/W R/W R/W Table 5-29. Rx Message: Msg Flags Register Definitions Bits Field Name 15:8...

  • Page 78: Error Count And Status Registers

    Error Count and Status Registers OFFSET FIELD RESET Table 5-31. Tx\Rx Error Count Register Definitions Bits Field Name 15:8 RE[7:0] TE[7:0] OFFSET FIELD RESET Bits Field Name 15:4 RX96 TX96 ES[1:0] Table 5-30. Tx/Rx Error Count Description Rx_er_cnt Bits The receiver error counter according to the Bosch CAN specification. When in bus off, this counter counts the idle states.

  • Page 79: Table 5-34. Tx/Rx Message Level Register

    Table 5-34. Tx/Rx Message Level Register OFFSET FIELD RESET Table 5-35. Tx/Rx Message Level Register Definitions Bits Field Name 15:4 RL[1:0] TL[1:0] Description Reserved rx_level[1:0] Sets the rx_msg interrupt threshold: 0 = at least 1 message in receive FIFO 1 = at least 2 messages in receive FIFO. 2 = at least 3 messages in receive FIFO.

  • Page 80: Interrupt Flags

    Interrupt Flags The following flags are set on internal events (they activate an interrupt line when enabled). They are cleared by writing a ‘ 1’ to the appropriate flag. Acknowledging the tx_msg interrupt also acknowledges all tx_xmit interrupt sources. Acknowledging one of the tx_xmit interrupt sources also acknowledges the tx_msg interrupt.

  • Page 81: Interrupt Enable Registers

    Interrupt Enable Registers All interrupt sources are grouped into three groups (traffic, error and diagnostics interrupts). To enable a particular interrupt, set its enable flag to ‘ 1’ . OFFSET FIELD RESET Table 5-39. Interrupt Enable Register Definitions Bits Field Name RX_MSG TX_MSG TX_XMIT2...

  • Page 82: Can Operating Mode

    Bits Field Name OVR_LOAD ARB_LOSS INT_ENB CAN Operating Mode The CAN modules can be used in different operating modes. By disabling transmitting data, it is possible to us the CAN in listen only mode enabling features such as automatic bit rate detection.

  • Page 83: Can Configuration Registers

    Note: The Loopback Mode register in CAN module 2 is not functional. For proper operation in loopback mode, the configuration of both CAN modules must be the same. CAN Configuration Registers The following registers set bit rate and other configuration parameters. OFFSET FIELD RESET...

  • Page 84: Table 5-44. Configuration Register

    OFFSET FIELD RESET Table 5-45. Configuration Register Definitions Bits Field Name OVR_MSG 14:12 TS[2_2:2_0] 11:8 TS[1_3:1_0] AUTO_RES CFG_SJW1 SAMP_MOD EDGE_MOD Table 5-44. Configuration Register Description Overwrite Last Message 1= when FIFO is full and a new message arrives it overwrites the message in RxMsg3 buffer.

  • Page 85: Figure 5-4. Bit Time, Time Quanta, And Sample Point Relationships

    The following relations exist for bit time, time quanta, time segments ½, and the data sampling point. Figure 5-4. Bit Time, Time Quanta, and Sample Point Relationships Bit Time tseg1 + 1 tseg2 + 1 time quanta (TQ) Sample Point Bittime = (1+ ( tseg1 + 1) + (tseg2 + 1)) x timequanta timequanta = (bitrate +1) / f e.g., for 1Mbps with f...

  • Page 86: Acceptance Filter And Acceptance Code Mask

    Acceptance Filter and Acceptance Code Mask Three programmable Acceptance Mask and Acceptance Code register (AMR/ACR) pairs filter incoming messages. The acceptance mask register (AMR) defines whether the incoming bit is checked against the acceptance code register (ACR). Table 5-46. Acceptance Filter Enable Register OFFSET FIELD RESET...

  • Page 87: Table 5-50. Acceptance Mask Register: Id 12

    Table 5-50. Acceptance Mask Register: ID 12 OFFSET FIELD RESET Table 5-51. Acceptance Mask Register: ID12 Definitions Bits Field Name 15:3 ID[28:13] Table 5-52. Acceptance Mask Register: Data 55 OFFSET FIELD RESET Table 5-53. Acceptance Mask Register: Data 55 Definitions Bits Field Name 15:0...

  • Page 88: Table 5-54. Acceptance Code Register

    OFFSET FIELD RESET Table 5-55. Acceptance Code Register Definitions Bits Field Name 15:0 ID[28:13] Table 5-56. Acceptance Mask Register: ID12 OFFSET FIELD RESET Table 5-57. Acceptance Mask Register: ID12 Definitions Bits Field Name 15:3 ID[12:0] Table 5-58. Acceptance Mask Register: Data 55 OFFSET FIELD RESET...

  • Page 89: Canbus Analysis

    CANbus Analysis Three additional registers are provided for advanced analysis of a CAN system. These registers include arbitration lost and error capture registers, as well as a CANbus frame reference register that contains information about the CANbus state and the physical Rx and TX pins. Arbitration Lost Capture Register The Arbitration Lost Capture register captures the most recent arbitration loss event with the frame reference pointer.

  • Page 90: Table 5-62. Error Capture Register

    Error Capture Register The Error Capture register captures the most recent error event with the frame reference pointer, rx- and tx-mode and the associated error code. OFFSET FIELD RESET Table 5-63. Error Capture Register Definitions Bits Field Name 15:13 Err[2:0] 12:8 FR[4:0] TX_MOD...

  • Page 91: Table 5-64. Frame Reference Register

    Frame Reference Register The Frame Reference register contains information of the current bit of the CAN message. A frame reference pointer indicates the current bit position. This enables message tracing on bit level. Note: The reset value of this register’s bits is indeterminate. OFFSET FIELD −...

  • Page 92: Can Bus Interface

    Bits Field Name FRB[5:0] CAN Bus Interface DSTni contains two complete CAN controllers, CAN0 and CAN1. Each controller supplies two signal pins, CAN receive (CAN_RX) and CAN transmit (CAN_TX). These signals are routed to interface circuits and a CAN transceiver such as the PCA82C251. From the transceiver, the signals become CAN- and CAN+, which are routed to CAN interface connectors.

  • Page 93: Figure 5-7. Power For Can

    You can also provide local isolated power for the transceiver circuits, as required when using CANopen. If you are using both DeviceNet and CANopen, use the jumpers to select between bus power (+5_BUS) or isolated power (ISO_PWR). The jumpers P_C05V and P_C0G will then provide +5_CAN and GND_CAN to the transceiver circuits.

  • Page 94: Figure 5-8. Can Transceiver And Isolation Circuits

    Figure 5-8. CAN Transceiver and Isolation Circuits +5v(F) 0.01uf R190 CAN_RX HCPL-0601 +5_CAN GND_CAN +3.3v 0.01uf R193 HCPL-O601 CAN_TX 0.01uf GND_CAN R189 CANL CANH 0.01uf R191 +5_CAN GND_CAN 0.01uf CAN- CAN+ PCA82C251 GND_CAN...

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