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EVOC CPC-1814CLD5NA-N User Manual

Dual core & wide temperature 6u compact pci motherboard
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CPC-1814CLD5NA-N
双核宽温 6U Compact PCI 主板
Dual Core & Wide Temperature 6U
Compact PCI Motherboard
Version: C02
 
 

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Summary of Contents for EVOC CPC-1814CLD5NA-N

  • Page 1     CPC-1814CLD5NA-N 双核宽温 6U Compact PCI 主板 Dual Core & Wide Temperature 6U Compact PCI Motherboard Version: C02    ...

  • Page 2: Copyright Notice

    Trademarks EVOC is a registered trademark of EVOC Intelligent Technology Co., Ltd. Other product names mentioned herein are used for identification purposes only and may be trademark and/or registered trademarks of their respective companies.

  • Page 3: Safety Instructions

      Safety Instructions Please read this manual carefully before using the product; Leave the board or card in the antistatic bag until you are ready to use it; Touch a grounded metal object (e.g. for 10 seconds) before removing the board or card from the anti-static bag;...

  • Page 4: Table Of Contents

      Contents  Chapter 1 Product Introduction ........1  Overview ........................1  Environment and Mechanical Dimensions ..............1  Typical Power Consumption..................2  Microprocessor ......................2  Chipset..........................2  Memory ........................2  Display Function......................2  LAN Function.......................2  Audio Function......................3  On-board IO........................3  Watchdog Function.......................3  Power Feature.......................3  Chapter 2 Installation ..........4  Product Outline......................4 ...
  • Page 5   LAN Port ........................11  Serial Port ........................12  GPIO Connector ......................13  Indicator........................13  Reset Button .......................13  Compact Flash Connector...................14  Compact PCI Connector .....................15  PMC Connector ......................19  Chapter 3 BIOS Setup ..........22  BIOS Overview ......................22  BIOS Parameter Setup....................22  Basic Function Setting for BIOS ................23  System Resource Managed by BIOS under X86 Platform .........33 ...

  • Page 6: Chapter 1 Product Introduction

    Chapter 1 Product Introduction   Chapter 1 Product Introduction Overview CPC-1814CLD5NA-N contains Intel® GME965 + Intel® ICH8M chipset, Intel® Core 2 Duo L7500 high-performance and low-power processor and dual-channel DDRII memory on-board, up to 2GB. As for graphics processing, it deploys Intel®...

  • Page 7: Typical Power Consumption

    Intel® GME965 chipset integrated with GMA X3100 graphics chip, supporting VGA display and LVDS and DVI alternative display with maximum resolution up to 1920x1080. Note: the rear IO boards, CPC-RP804B and CPC-RP804R, support DVI display with 1024x768 maximum resolution. - 2 - CPC-1814CLD5NA-N  ...

  • Page 8: Lan Function

    One HD Audio connector brought out via rear IO board. On-board IO  Two serial ports (CPC-1814CLD5NA-N has one on board while the IO board brings out the other one; the serial port on rear IO board supports RS-232/RS-422/RS-485 mode);...

  • Page 9: Chapter 2 Installation

    Please adopt appropriate screws and proper installation methods (including board allocation, CPU and heat sink installation, etc); otherwise, the board may be damaged. It is recommended to use GB 818 M2.5x5 screws at PH1 ~ PH4 and PTH5 ~ PTH10. - 4 - CPC-1814CLD5NA-N  ...

  • Page 10: Locations Of Connectors

      Chapter 2 Installation   Locations of Connectors VGA1 LAN1 COM1 USB2 USB1 RST1 PTH6 PTH7 JTAG1 SATA1 PTH10 PTH5 GPIO1 PMC1 LPC1 JCF1 PTH9 PTH8 CPC-1814CLD5NA-N - 5 -  ...

  • Page 11: Structure

    Tip: How to identify the first pin of the jumpers and connectors Observe the letter beside the socket, it would be marked with “1” or bold lines or triangular symbols; Observe the solder pad on the back; the square pad is the first pin. - 6 - CPC-1814CLD5NA-N  ...

  • Page 12: Jumper Setting

    66MHz. (Default: 2=ON; 3=OFF; 4=OFF) Note: When CPC-8408B-A089 complete PC is used, the default setting for SW1 Pin4 on the motherboard is 4=ON. (Default: 2=ON, 3= OFF, 4=ON). CPC-1814CLD5NA-N - 7 -  ...

  • Page 13: Cpci Hot-Swappable Micro-Switch

    Note: forward mode indicates that the PI7C9x13 Bridge is converted from PCIE to PCI bus while backward mode indicates that the PI7C9x13 Bridge is converted from PCI to PCIE bus. CPCI Hot-swappable Micro-switch Signal Name VCC3 EJECT (Pitch: 1.25mm) - 8 - CPC-1814CLD5NA-N  ...

  • Page 14: Jtag Connector

    Record the data required by CPLD via JTAG1 on-board. Signal Name JTAG1 (Pitch: 2.54mm) Setup Function [1-2] Short Reset PCIe signal (Default) JP7 (Pitch: 2.0mm) [2-3] Short Reset PCI signal The board provides two standard USB ports. Signal Name USB_Data- USB_Data+ USB1/USB2 CPC-1814CLD5NA-N - 9 -  ...

  • Page 15: Lpc Connector

    Note: when using with the rear IO boards, CPC-RP804B&CPC-RP804R, please pay attention that the VGA connector of the rear IO board and that of the motherboard are alternative, so as to avoid asynchronous display or other problems. - 10 - CPC-1814CLD5NA-N  ...

  • Page 16: Sata Connector

    LAN. Please refer to the status description for each LED: MX0, MX0-: positive/negative data MX1, MX1-: positive/negative data channel 0 channel 1 MX2, MX2-: positive/negative data MX3, MX3-: positive/negative data channel 2 channel 3 ACTLED: LAN activity status indicator LILED: LAN linked status indicator CPC-1814CLD5NA-N - 11 -  ...

  • Page 17: Serial Port

    The board provides a serial communication connector (RJ45), which can connect with devices with standard RS-232 connectors, such as mouse, modem and digital camera, etc. Signal Name RTS# DTR# COM1 DSR# CTS# Note: the serial port doesn’t support wake-up function. - 12 - CPC-1814CLD5NA-N  ...

  • Page 18: Gpio Connector

    Description Hard disk is idle Hard disk is operating Power failure Power normal Normal operating status At hot-swapping status Cannot operate watchdog Operate the watchdog Reset Button Signal Name Signal Name RESET# GND_Chassis GND_Chassis RST1 CPC-1814CLD5NA-N - 13 -  ...

  • Page 19: Compact Flash Connector

    The CF card is at Master status in system. The pin definitions of the Compact Flash slot are as follows (Marked as CF1 in figure). Signal Name Signal Name CD1# CS0# CS1# VS1# ATASEL# IOR# IOW# CSEL# VS2# RESET# IORDY DREQ DACK# DASP# ATA66_DET WP/IOCS16# CD2# - 14 - CPC-1814CLD5NA-N  ...

  • Page 20: Compact Pci Connector

    KEY AREA +3.3V FRAME# IRDY# BD_SEL# TRDY# DEVSEL# V(I/O) STOP# LOCK# +3.3V IPMB_SCL IPMB_SDA PERR# SERR# +3.3V C/BE1# +3.3V AD15 AD14 AD13 AD12 V(I/O) AD11 AD10 +3.3V M66EN C/BE0# +3.3V +3.3V V(I/O) ACK64# REQ64# ENUM# +3.3V CPC-1814CLD5NA-N - 15 -  ...
  • Page 21 AD51 AD50 AD56 AD55 AD54 AD53 AD59 V(I/O) AD58 AD57 AD63 AD62 AD61 AD60 C/BE5# 64EN# V(I/O) C/BE4# PAR64 V(I/O) C/BE7# C/BE6# CLK4 GNT3# REQ4# GNT4# CLK2 CLK3 SYSEN# GNT2# REQ3# CLK1 REQ1# GNT1# REQ2# - 16 - CPC-1814CLD5NA-N  ...
  • Page 22 PCIE_TXP3 PCIE_RXP4 PCIE_TXP5 SATA_TXN1 PCIE_RXP3 PCIE_TXN3 PCIE_TXN5 SATA_TXP1 PCIE_TXP4 LA_CLKP LA_DATAP3 PCIE_TXN4 LANA_LINK1000# SATA_RXN2 LA_CLKN LA_DATAN3 LANB_LINK1000# SATA_RXP2 LA_DATAP2 LA_DATAP0 LA_DATAP1 LA_DATAN2 LANA_LINK100# SATA_TXN2 LA_DATAN0 LA_DATAN1 LANB_LINK100# SATA_TXP2 SMB_CLK LAN4_RST# L_VDDEN SMB_DATA LA_BKLT_CTRL LA_BKLT_EN GND CPC-1814CLD5NA-N - 17 -  ...
  • Page 23 USB3N ACZ_SYNC KB_CLK ACZ_SDIN0 ACZ_SDOUT ACZ_BITCLK KB_DATA ACZ_RST# CRT_RED CRT_GREEN CRT_BLUE CRT_HSYNC CRT_VSYBC CRT_DDC_DATA CRT_DDC_CLK COM2_TXD COM2_DSR# COM2_DTR# ACZ_DET# COM2_RI# COM2_RXD COM2_RTS# COM2_CTS# COM2_DCD# VCC5 VCC3_3 VCC3_3 VCC3_3 LAN5_RST# VCC5 VCC3_3 MS_DATA VCC3_3PWRGD VCC12 MS_CLK - 18 - CPC-1814CLD5NA-N  ...

  • Page 24: Pmc Connector

    JN1, JN2 and JN4 are PCI expansion slots. The definitions of JN1 are as follows: Signal Name Signal Name FRAME# -12V PIRQA# IRDY# PIRQB# DEVSEL# PIRQC# PLOCK# PIRQD# +3.3V CLK1 AD15 AD12 GNT0# AD11 REQ0# AD31 C/BE0# AD28 AD27 AD25 C/BE3# AD22 AD21 AD19 AD17 REQ64# CPC-1814CLD5NA-N - 19 -  ...
  • Page 25 +3.3V STOP# PERR# +3.3V SERR# C/BE1# +3.3V RST# AD14 AD13 +3.3V M66EN AD10 PME# +3.3V AD30 AD29 REQ_B(1) +3.3V AD26 GNT_B#(1) AD24 +3.3V IDSEL AD23 EREADY(1) +3.3V AD20 RSTOUT#(1) AD18 ACK64# +3.3V AD16 C/BE2# Monarch#(1) - 20 - CPC-1814CLD5NA-N  ...
  • Page 26 Signal Name Signal Name Notes for JN1 ~ JN4: the default setting of VIO signal is to connect with +3.3V via 0Ω resistor; therefore, please do not connect the +5V PMC with the PMC slot. CPC-1814CLD5NA-N - 21 -  ...

  • Page 27: Chapter 3 Bios Setup

    Please use the internal default value of BIOS to restore the system. Our company is constantly researching and updating BIOS, its setup interface may be a bit different. The figure below is for reference only; it may be different from your BIOS setting in use. - 22 - CPC-1814CLD5NA-N  ...

  • Page 28: Basic Function Setting For Bios

    Choose this option and set the current date by < + > / < - >, which is displayed in the format of month/date/year. Reasonable range for each option is: Month (Jan.-Dec.), Date (01-31), Year (Maximum to 2099), Week (Mon. ~ Sun.). CPC-1814CLD5NA-N - 23 -  ...
  • Page 29 :800MHz Tab Select Field Cache L1; :64 KB General Help F10 Save and Exit Cache L2; :4096KB ESC Exit Ratio Actual Value Intel(R) Virtualization TECH [Enabled] Core Multi-Processing [Enabled] V02.61 (c)Copyright 1985-2006, American Megatrends, Inc - 24 - CPC-1814CLD5NA-N  ...
  • Page 30 Both RAID and AHCI functions require supports from hardware chip and OS.  Primary ~ Fourth IDE Master/Slave ﹡Type Not Installed: no IDE device can be detected by system; AUTO: automatic detection of IDE parameters when power on; CPC-1814CLD5NA-N - 25 -  ...

  • Page 31: Dma Mode

    ←→ Select Screen Serial Port1 Address [3F8/IRQ4] ↑↓ Select Item Serial Port2 Address [2F8/IRQ3] + - Change Field Tab Select Field General Help F10 Save and Exit ESC Exit V02.61 (c)Copyright 1985-2006, American Megatrends, Inc. - 26 - CPC-1814CLD5NA-N  ...
  • Page 32 : 11.481V F10 Save and Exit ESC Exit VBAT : 3.200 V V02.61 (c)Copyright 1985-2006, American Megatrends, Inc.  System Temperature Current system temperature, it is monitored by thermal resistor on motherboard.  CPU Temperature CPC-1814CLD5NA-N - 27 -  ...
  • Page 33 Legacy USB Support This option is used to support legacy USB devices; when this option is set to Enabled, the USB device could be used even if under OS that doesn’t support USB, such as DOS. - 28 - CPC-1814CLD5NA-N  ...
  • Page 34 Configure the frequency for DRAM; it is recommended to use automatic modification instead of manual modification; otherwise, it will not be able to power on because it is not supported by DRAM.  Configure DRAM Timing by SPD CPC-1814CLD5NA-N - 29 -  ...
  • Page 35 F10 Save and Exit IRQ14 [Available] ESC Exit IRQ15 [Available] V02.61 (c)Copyright 1985-2006, American Megatrends, Inc.  IRQ3 ~ 15 This option is used to specify whether the IRQ number is PNP mode or reserved for ISA. - 30 - CPC-1814CLD5NA-N  ...
  • Page 36 Supervisor Password :Not Installed ←→ Select Screen User Password :Not Installed ↑↓ Select Item Enter Change General Help Change Supervisor Password F10 Save and Exit ESC Exit Change User Password V02.61 (c)Copyright 1985-2006, American Megatrends, Inc. CPC-1814CLD5NA-N - 31 -  ...
  • Page 37  Load Optimal Defaults This menu is used to input default value in system configuration. These default values are optimized and could give play to the high capability of all hardware. - 32 - CPC-1814CLD5NA-N  ...

  • Page 38: System Resource Managed By Bios Under X86 Platform

    28 interrupt sources, such as motherboard supporting PCI-X. However, relevant OS are required to enable that function, and currently, only the OS above Windows 2000 could support that function. CPC-1814CLD5NA-N - 33 -  ...
  • Page 39 Motherboard Resource 087h DMA Controller #3 088h Motherboard Resource 089h - 08Bh DMA Controller #4 08Ch - 08Eh Motherboard Resource 08Fh DMA Controller #5 090h - 09Fh Motherboard Resource 0A0h - 0A1h Programmable Interrupt Controller #2 - 34 - CPC-1814CLD5NA-N  ...
  • Page 40 480h - 4BFh Motherboard Resource 4D0h –4D1h Motherboard Resource 800h - 87Fh Motherboard Resource B00h-B0Fh Motherboard Resource B10h-B1Fh Motherboard Resource A79h ISAPNP Read Data Port D000h-DFFFh Intel(R) ICH8 Family PCI Express Root Port-2849 0D00h-FFFFh PCI bus CPC-1814CLD5NA-N - 35 -  ...
  • Page 41 Reserved for hot-swap IRQ6 Standard FDD Controller IRQ7 Reserved IRQ8 System CMOS/Real Time Clock IRQ9 Software Transfer to Int 0Ah IRQ10 Reserved IRQ11 Reserved IRQ12 Mouse Connector IRQ13 Numeric co-processor IRQ14 Primary IDE IRQ15 Secondary IDE - 36 - CPC-1814CLD5NA-N  ...

  • Page 42: Appendix

    #define INPUT4 3 #define OUTPUT1 0 #define OUTPUT2 1 #define OUTPUT3 2 #define OUTPUT4 3 BAR= 0x500; input[]={1,6,7,38}; //PIN defining GPI output[]={20,22,27,28}; //PIN defining GPO for (i=0;i<=3;i++) //Initialize and organize GPIO initializ_gpio(input[i]); initializ_gpio(output[i]); set_in_out(1,input[i]); set_in_out(0,output[i]); CPC-1814CLD5NA-N - 37 -  ...
  • Page 43 Function Name: GPIO initialization function initializ_gpio(int pin_NO) Input Parameters: (PIN number) Functions: initialize GPIO according to DATASHEET specification *************************************************************/ void initializ_gpio(int pin_NO) unsigned int ioadd=(BAR+0x00); unsigned char mask; int offset=pin_NO/8; unsigned char tempv; //********************* if(pin_NO>=32) ioadd=(BAR+0x30); offset=(pin_NO-32)/8; //********************* while(offset!=0) - 38 - CPC-1814CLD5NA-N  ...
  • Page 44 //the calculation of the function is the same as that of initializ_gpio(int pin_NO) unsigned int ioadd=(BAR+0x04); unsigned char mask; int offset=pin_NO/8; unsigned char tempv; if(pin_NO>31) ioadd=(BAR+0x34); offset=(pin_NO-32)/8; while(offset!=0) ioadd++; offset--; CPC-1814CLD5NA-N - 39 -  ...
  • Page 45 Input Parameters: (high/low level, PIN number)(high_low=1 high level, =0 low level Returned Value: Functions: initialize GPIO according to DATASHEET specification *************************************************************/ void write_gpio(const int high_low, const int pin_NO) unsigned int ioadd=(BAR+0x0c); int offset=pin_NO/8; unsigned char mask; unsigned char tempv; if(pin_NO>=32) ioadd=(BAR+0x38); - 40 - CPC-1814CLD5NA-N  ...
  • Page 46 Function Name: read the function of the input pin read_gpio(int pin_NO) Input Parameters: (,pre-set value, PIN number) Returned Value: return the current PIN value, or Functions: return the current PIN value *************************************************************/ unsigned char read_gpio(const int pin_NO) int read_v; CPC-1814CLD5NA-N - 41 -  ...
  • Page 47 If the input pin is low level, the IO value is normal; vice versa. Set the output pin to high level in the same way, short circuit and measure the output pin to check whether it is high level. - 42 - CPC-1814CLD5NA-N  ...

  • Page 48: Watchdog Programming Guide

    0x87); outportb(INDEX_PORT, 0x87); outportb(INDEX_PORT, 0x07); outportb(DATA_PORT, 0x08); outportb(INDEX_PORT, 0x30); outportb(DATA_PORT, 0x01); (2) Configure WDT operating mode, reset mode or interrupt mode: unsigned char oldval; outportb(INDEX_PORT,0x2d); oldval = inportb(DATA_PORT); a. Configure WDT to reset mode CPC-1814CLD5NA-N - 43 -  ...
  • Page 49 Time by second: outportb(INDEX_PORT,0xf5); outportb(DATA_PORT,0x00); (4) Enable/Disable WDT a. Enable WDT: outportb(INDEX_PORT,0xf6); outportb(DATA_PORT,TIME_OUT_VALUE); /*Please replace constant TIME_OUT_VALUE with the unit number of timeout value (0x01 ~ 0xFF)*/ b. Disable WDT: outportb(INDEX_PORT,0xf6); outportb(DATA_PORT,0x00); - 44 - CPC-1814CLD5NA-N  ...

  • Page 50: Troubleshooting And Solutions

    Remove the two pins to their original location with well. tweezers carefully, insert the memory, reboot the system and the system will be booted smoothly. CPC-1814CLD5NA-N - 45 -  ...
  • Page 51 OK. Re-install detected. the device driver and check whether it can be recognized; check whether the device is normal; if the device is normal, then check whether the device is compatible with the motherboard.   - 46 - CPC-1814CLD5NA-N  ...

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