Pc I/F Block Diagram - Pioneer PDP-R03E Service Manual

1
PDP-R03E

3.1.5 PC I/F BLOCK DIAGRAM

A
B
29,3
25,2
21,2
13,1
9,10
C
5,6
D
Y 39..32
C 30 ..23
16
1
2
CPCI-00 56CE
12 CLR_ SW
7 PC _H
P C_V
9
P C_C
10
5
1
3
MAIN _H
D
MAIN_VD
HV SEL
P C_R
18
PC _G
17
P C_B
MAI N_
R
0
MAI N_
G
6
MAI N_
B
2
12V->9V R eg
IC415 B A09FP
VIDEO SIGNAL
PEAK DETECTION
ACL_S IG
OV0_CLP
SUB _Y
4
SUB_ Cb
SUB_ Cr
V1 ADC
3.27V
RT, RB SETTING
1.17V
CIRCUIT
2
1
About 60MHz
5 THERMO
6 BSREQ
19
CD_ HD
18
CD _VD
21
CD_CLK
SEL _CD
12
TXD 1_T
14
RXD 1_T
11 CAR D_RST
16 P XOE
2
3
1B
1Y
OV0 _H
2B
2Y OV0_V
4B V0
4Y PC_ C3
Sync
Sel
1A
2A
IC411
74LCX157
4A
CXA3506R
VCO
WHISKER
CORRECTIO
-A /+B
N CIRCUIT
IC423, IC424
12V->5VReg
IC7 PQ0 5TZ11
RIN2 SYNCIN1
GIN2 SYNCIN2
BIN2 HOLD
CLPIN
RIN1
V0
OV0_HSC2
DIVOUT
A/D
GIN1
OVCLK(Max60MHz)
1/2C LK
Amp
BIN1
PLL
RA[7..0]
RB[7..0]
IC4
CXA3506R
GA[7..0]
ROUT
GB[7..0]
2
I C=CH2
GOUT
BA[7..0]
BOUT
BB[7. .0]
XPOWERSAVE XPW R_SV
5V->3.3V Reg
IC8 PQ2 0VZ11
AIN AO[8..1]
BIN BO[8..1]
V1
A/D
CIN CO[8..1]
IC310 OV1_VCKO
.
RT CLK
( = 15M
.
TLC57 33A
OV1_CLP
RB EXTCLP
- OE SAD C_OE
V1 OV1_HSNR
FIN-A
PLL
OV1_HSNF
FIN-B
VCOOUT
IC328 OV1_PDEN
PFDINH
TLC 2933IPW
1A
1Y
OV1 _H
2A
V1
2Y
OV1_V
Sync&
4A
4Y
Clock
OV1_VCLK
1B
Sel
2B
IC421
4B
74LCX157
-A /+B
3
4
X4
25MHz
MCK_REF
V0_HSYNC
V0_VSYNC
V0_CSYNC
OV0_PDEN
V0_PDEN
V0_HSYNR
OV0_CLP
V0_CLP
V0_HSYNC2
V0_VDCLK_I
8
V0_RA[7..0]
8
V0_RB[7..0]
CVIC
8
V0_GA[7.. 0 ]
8
V0_GB[7..0]
8
V0_BA[7..0]
IC25
8
V0_BB[7..0]
8
V1_GA[7.. 0 ]
8
V1_BA[7..0]
8
V1_RA[7..0]
V1_VDCLK_O
Hz)
V1_CLP
V1_HSYNR
V1_HSYNF
V1_PDEN
V1_HSYNC
V1_VSYNC
V1_VDCLK_I
SDRAM BUS
D:128,A:11,BA:2,Ctrl:13
SDCLK=100MHz
SDRAM
512Kx128bitx4 BANK
IC319-322
HY57V653220BTC-7 4 PCS.
4
DCLK
DO_RA[9.. 2 ]
DO_GA[9.. 2 ]
DO_BA[9..2]
LCLK
DO_HSYNC
DO_VSYNC
DO_HDISP
BINT
BCLK
XBCS
BWAIT
XRESET
PLL_S
BD,BA