Pc/If Block Diagram - Pioneer PDP-R03U Service Manual

1

3.5 PC/IF BLOCK DIAGRAM

QQ
3 7 63 1515 0
CPCI-00 56CE
A
12 CLR_ SW
7
9
10
5
1
3
B
18
17
29,3
0
25,2
6
21,2
2
C
TE
L 13942296513
ACL_S IG
13,1
D
4
9,10
5,6
2
1
E
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F
18
1
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2
PC _H 1B
P C_V
2B
P C_C
4B
1A
2A
MAIN _H
74LCX157
4A
D
MAIN_VD
HV SEL -A /+B
P C_R
PC _G
P C_B
RIN2
GIN2
BIN2
MAI N_
RIN1
R
MAI N_
GIN1
G
MAI N_
BIN1
B
12V->9V R eg
IC415 B A09FP
ROUT
VIDEO SIGNAL
GOUT
PEAK DETECTION
BOUT
OV0_CLP
5V->3.3V Reg
IC8 PQ2 0VZ11
SUB _Y AIN
SUB_ Cb BIN
SUB_ Cr CIN
V1 ADC
3.27V
RT
RT, RB SETTING
1.17V
RB
CIRCUIT
About 60MHz
VCOOUT
TLC 2933IPW
x ao
. i
2
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3
X4
25MHz
1Y
OV0 _H
2Y OV0_V
V0
4Y PC_ C3
Sync
Sel
IC411
CXA3506R
VCO
WHISKER
CORRECTIO
N CIRCUIT
IC423, IC424
12V->5VReg
IC7 PQ0 5TZ11
SYNCIN1
SYNCIN2
HOLD
OV0_CLP
CLPIN
V0
OV0_HSC2
DIVOUT
A/D
OVCLK(Max60MHz)
1/2C LK
Amp
8
PLL
RA[7..0]
8
RB[7..0]
IC4
8
CXA3506R
GA[7..0]
8
GB[7..0]
2
I C=CH2
8
BA[7..0]
Q Q
3 6 7
8
BB[7. .0]
XPOWERSAVE XPW R_SV
AO[8..1]
BO[8..1]
V1
A/D
CO[8..1]
IC310 OV1_VCKO
CLK
( 15M Hz)
TLC57 33A
OV1_CLP
EXTCLP
- OE SAD C_OE
V1
OV1_HSNR
FIN-A
PLL
OV1_HSNF
FIN-B
IC328 OV1_PDEN
PFDINH
OV1 _H
OV1_V
OV1_VCLK
u163
y
PDP-R03U
3
4
2 9 9 4
8
MCK_REF
V0_HSYNC DO_RA[9.. 2 ]
V0_VSYNC DO_GA[9.. 2 ]
V0_CSYNC DO_BA[9..2]
DO_HSYNC
OV0_PDEN
V0_PDEN
DO_VSYNC
V0_HSYNR
V0_CLP
V0_HSYNC2
V0_VDCLK_I
V0_RA[7..0]
V0_RB[7..0]
CVIC
V0_GA[7.. 0 ]
V0_GB[7..0]
V0_BA[7..0]
1 3 1 5 0 5 IC25 8 2 9
V0_BB[7..0]
8
V1_GA[7.. 0 ]
8
V1_BA[7..0]
8
V1_RA[7..0]
V1_VDCLK_O
V1_CLP
V1_HSYNR
V1_HSYNF
V1_PDEN
V1_HSYNC
V1_VSYNC
V1_VDCLK_I
SDRAM BUS
D:128,A:11,BA:2,Ctrl:13
m
SDCLK=100MHz
co
.
SDRAM
512Kx128bitx4 BANK
IC319-322
HY57V653220BTC-7 4 PCS.
4
2 8
9 9
DCLK
LCLK
DO_HDISP
BINT
9 4 2 8 9 9
BCLK
XBCS
BWAIT
XRESET
PLL_S
BD,BA