Pioneer DVR-104 Service Manual page 52

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QQ K4S161622D-TC60 (R4 MAIN ASSY : IC231)
3 7 63 1515 0
SDRAM
A Block Diagram
Bank Select
CLK
ADD
B
LCKE
LRAS LCBR
CLK CKE
C
Pin Function
TE
L 13942296513
Pin
CLK System Clock
CS Chip Select
D
CKE Clock Enable
A ~ A /AP Address
0 10
BA Bank Select Address
RAS Row Address Strobe
CAS Column Address Strobe
E
WE Write Enable
L(U)DQM Data Input/Output Mask
DQ ~ Data Input/Output
0 15
V /V Power Supply/Ground
DD SS
www
V /V Data Output Power/Ground
DDQ SSQ
No Connection/
N.C/RFU
Reserved for Future Use
F
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Latency & Burst Length
Programming Register
LWE LCAS
Timing Register
CS RAS CAS WE
Samsung Electronics reserves the right to
*
change products or specification without
notice.
Name
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
x ao
immunity.
y
This pin is recommended to be left No Connection on the device.
. i
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8
Data Input Register
512K x 16
512K x 16
Column Decoder
LWCBR LDQM
L(U)DQM
Q Q
3 6 7 1 3
Input Function
~ RA , column address : CA
0 10
after the clock and masks the output.
SHZ
u163
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DVR-104
3
4
2 9 9 4 2 8
Pin Assignment
LWE
(TOP VIEW)
LDQM
V 1 50 V
DD
DQ0 2 49 DQ15
DQ1 3 48 DQ14
V 4 47 V
DQi
SSQ
DQ2 5 46 DQ13
DQ3 6 45 DQ12
V 7 44 V
DDQ
DQ4 8 43 DQ11
DQ5 9 42 DQ10
V 10 41 V
SSQ
DQ6 11 40 DQ9
DQ7 12 39 DQ8
V 13 38 V
DDQ
LDQM 14 37 N.C/RFU
WE 15 36 UDQM
CAS 16 35 CLK
RAS 17 34 CKE
CS 18 33 N.C
BA 19 32 A9
A10/AP 20 31 A8
A0 21 30 A7
A1 22 29 A6
A2 23 28 A5
A3 24 27 A4
V 25 26 V
DD
1 5 0 5 8 2 9 9 4
~ CA
0 7
m
co
4
9 9
SS
SSQ
DDQ
SSQ
DDQ
SS
2 8 9 9