Table of Contents
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A
B
C
SCHEMATIC DIAGRAMS
DSP 1/3
1
2
DIGITAL IN
CB502
1.9
Page 175
B2
1.9
0
0
3.3
to AVIDEO (3)_W701
IC501
3.3
0
0
0
3
CB503
3.3
3.3
0
3.3
(Writing port)
3.3
3.3
3.3
0
3.3
SDRAM
3.3
3.3
0.1
3.3
0.1
3.3
0.7
3.3
0.1
3.3
0.1
3.3
4
0.8
3.3
0.2
3.3
0.2
3.3
0.1
3.3
3.3
0.8
0.8
3.3
0.2
0.1
0.1
0
0.1
0
0
0.1
0.8
0
1.5
0
0.7
0
0.1
0
0.7
0
0.8
0
0.1
0
0.2
0
IC505
0
0.8
0.8
0.8
0.8
0.1
0.2
0
2.0
3.9
5
3.0
3.3
3.3
3.0
3.3
0.1
3.3
0
3.3
0.1
0
0.5
2.0
1.8
3.3
1.7
1.3
2.1
2.1
0
1.1
6
7
0
1.7
0
0
1.2
0.1
3.3
0
0
0
3.3
0
1.2
8
1.7
0
3.3
1.2
0
0
0
1.2
0
3.3
3.3
No replacement part available.
3.3
0
3.3
3.3
1.2
3.3
3.3
0
9
3.3
4.2
IC516
10
D
E
F
DSP #1
DAF
DAS
DAC/SW
DASB
0
1.7
0
1.3
0
3.3
0
0
3.3
0
3.3
0
3.3
0
3.3
1.3
3.3
1.7
3.3
3.3
0
3.3
3.3
3.3
0
3.3
3.3
1.3
0
3.3
3.3
0
3.3
0
0
0
IC503
1.3
0
3.3
0
No replacement part available.
3.3
0
No replacement part available.
3.3
3.3
1.3
3.3
3.3
0
3.3
0
3.3
0
3.3
0
3.3
0
3.3
0
3.3
0
3.3
0
3.3
0
3.3
0
3.3
0
0
3.3
3.3
0
3.3
0
3.3
0
3.3
0
0
3.3
3.3
0
3.3
0
3.3
0
3.3
0
0
1.2
0
1.2
0
1.2
0
1.2
0
0
1.2
1.2
0
1.2
0
1.2
0
0
1.2
1.2
0
1.2
0
1.2
0
1.2
0
1.2
0
1.2
0
1.3
1.2
0
1.3
IC507
1.2
0
1.3
1.2
0
0.7
1.2
0
1.4
1.2
0
0
0
1.2
0
0
0
0
3.3
0
0
0
0
0
0
0
0
0
0
0
DSP #1
DSP #1
BUFFER
1.7
0
1.7
0
1.7
0
1.7
0
0
0
0
0
0
0
3.3
0
3.3
0
1.6
0
0
1.7
1.7
0
1.7
1.3
0
0
3.3
0
0
3.3
0
0
1.7
0
3.3
0
3.3
3.3
0
DSP #3
3.3
3.3
1.2
0
3.3
0
3.3
0
3.3
3.3
0
1.2
0
0
3.3
1.2
3.3
0
0
3.3
0
0
0
1.2
0
0
0
3.3
SDRAM
IC511
1.2
1.9
G
H
IC501: TC7SH08FU
2-input AND gate
IN B
1
IN A
2
GND
3
IC505: W9864G2GH-7
3.3
128/64 M SDRAM
3.3
DASW
0
3.3
CLK
DSP #2
0
3.3
1.3
CKE
3.3
0
3.3
0
CS
3.3
0
RAS
COMMAND
3.3
CAS
3.3
3.3
WE
0
1.3
0
0
A10
0
3.3
1.3
A0
0
3.3
0
A9
3.3
BS0
3.3
BS1
3.3
0
1.3
0
0
0
3.3
REFRESH
COUNTER
SDRAM
1.9
IC508
1.9
1.9
5.0
5.0
DAF
DAS
DAC
DASB
DASW
0
3.3
3.3
0
0.1
DSP #4
3.3
0
1.3
3.3
1.2
1.2
3.3
3.3
0
3.3
3.3
0
0
0
0
3.3
0
0
0
1.2
3.3
1.7
3.3
0
0
3.3
1.2
1.2
0
0
0
0
0
0
3.3
1.2
1.2
2.4
0
1.2
3.3
0
3.3
3.3
No replacement part available.
3.3
1.8
0
0
0
3.3
3.3
1.2
1.2
0
3.3
0
0
3.3
0
3.3
SDRAM
1.9
1.2
1.2
1.9
IC515
1.2
1.9
IC517
0.7
5.0
1.3
5.0
I
J
K
5
V
CC
4
OUT Y
IC503, 512, 513: SN74LVC245APWR
Octal bus transceivers with 3-state outputs
CLOCK
BUFFER
DIR
A1
CONTROL
SIGNAL
A2
GENERATOR
DECODER
A3
COLUMN DECODER
COLUMN DECODER
V
CC
1
86
V
SS
DQ0
2
85
DQ15
A4
V
CC
Q
3
84
V
SS
Q
DQ1
4
83
DQ14
CELL ARRAY
CELL ARRAY
BANK #0
BANK #1
DQ2
5
82
DQ13
A5
V
SS
Q
6
81
V
CC
Q
DQ3
7
80
DQ12
MODE
DQ4
8
79
DQ11
78
REGISTER
V
cc
Q
9
V
SS
Q
A6
SENSE AMPLIFIER
SENSE AMPLIFIER
DQ5
10
77
DQ10
ADDRESS
DQ6
11
76
DQ9
BUFFER
V
Q
12
75
V
Q
SS
CC
DQ7
13
74
DQ8
A7
NC
14
73
NC
V
CC
15
72
V
SS
DQM0
16
71
DQM1
A8
WE
17
70
NC
DQ0
CAS
18
69
NC
DATA CONTROL
DQ
RAS
19
68
CLK
CIRCUIT
BUFFER
DQ31
CS
20
67
CKE
GND
NC
21
66
A9
COLUMN
BS0
22
65
A8
COUNTER
DQM0–3
BS1
23
64
A7
A10/AP
24
63
A6
A0
25
62
A5
A1
26
61
A4
A2
27
60
A3
DQM2
28
59
DQM3
V
29
58
V
CC
SS
NC
30
57
NC
COLUMN DECODER
COLUMN DECODER
DQ16
31
56
DQ31
V
Q
32
55
V
Q
SS
CC
DQ17
33
54
DQ30
DQ18
34
53
DQ29
CELL ARRAY
CELL ARRAY
V
CC
Q
35
52
V
SS
Q
BANK #2
BANK #3
DQ19
36
51
DQ28
DQ20
37
50
DQ27
V
SS
Q
38
49
V
CC
Q
DQ21
39
48
DQ26
SENSE AMPLIFIER
SENSE AMPLIFIER
DQ22
40
47
DQ25
V
CC
Q
41
46
V
SS
Q
DQ23
42
45
DQ24
V
CC
43
44
V
SS
IC508, 511: W9816G6CH-7
IC506, 510, 514: D70YE101BRFP266
512 K x 2 banks x 16-bit SDRAM
Floating-point digital signal processors
Program/Data
JTAG EMU
256
RAM
CLK 35
D1
CLOCK
256K Bytes
McASP0
BUFFER
Data
64
32
16 Serializes
R/W
Program/Data
CKE 34
C67x+ Microprocessor
256
ROM Page1
256K Bytes
32
D2
Memory
Data
64
Controller
32
COLUMN DECODER
Program/Data
CS
18
CONTROL
R/W
ROM Page2
McASP1
256
6 Serializes
SIGNAL
R
256K Bytes
32
RAS
17
GENERATOR
O
Program
COMMAND
W
I/O
INT
Fetch
Program/Data
CAS
16
DECODER
32
D
ROM Page3
McASP2
256
WE
15
E
256K Bytes
2 Serializes
C
32
DIT Only
O
D
E
Program
CSP
32
32
R
32
SPI1
A10 20
256
Cache
SENSE AMPLIFIER
PMP DMP
32K Bytes
32
SPI0
32
32
32
I2C0
MODE
A0
21
REGISTER
High-performance
Crossbar Switch
32
A3
24
ADDRESS
32
I2C1
BUFFER
A4
27
32
32
32
32
32
RTI
A9
32
32
PLL
BA
19
I/O
Interrupts
MAX0
CONTROL
MAX1
Events
Out
In
EMIF
dMAX
Peripheral Interrupt and DMA Events
REFRESH
COLUMN
COLUMN DECODER
COUNTER
COUNTER
R
O
W
D
E
C
O
D
E
R
SENSE AMPLIFIER
IC517: W9864G6GH-7
IC516: R1171J331D-T1-F
64 M x 4 banks SDRAM
Voltage regulator
CLK
CLOCK
BUFFER
V
DD
5
1
V
OUT
CKE
CS
3
GND
RAS
Vref
CAS
WE
Current Limit
CE
2
4
GND
A10
A0
MODE
Pin No.
Symbol
Description
REGISTER
1
V
Output Pin of Voltage Regulator
OUT
A9
A11
2
CE
Chip Enable Pin
BS0
GND
Ground Pin
BS1
3
4
GND
Ground Pin
5
V
DD
Input Pin
REFRESH
COLUMN
COUNTER
COUNTER
# All voltages are measured with a 10MΩ/V DC electronic voltmeter.
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
L
M
N
RX-Z11/DSP-Z11
IC505, 515: BD3508EKN-E2
1-channel series regulator driver IC
VCC
1
20
Vcc
VCC
6
VIN1
2
19
OE
VCC
8
VIN2
VIN
UVLO
Current
EN
CL
9
Reference
Limit
VIN3
7
3
18
B1
Block
10
VCC
Vo1
16
Vo2
4
17
B2
17
Vo
Vo3
18
CL
UVLO
EN
R2
5
16
B3
TSD
Thermai
FB
Shutdown
19
GATE
R1
6
15
B4
TSD
NRCS
11
20
1
2
NRCS
GND
7
14
B5
8
13
B6
9
12
B7
10
11
B8
IC504: D710E001BZDH300
Floating-point digital signal processors
Program/Data
JTAG EMU
256
RAM
D1
256K Bytes
McASP0
Data
64
32
16 Serializers
R/W
Program/Data
C67x+ Microprocessor
256
ROM Page1
32
256K Bytes
D2
Memory
Data
64
32
Controller
Program/Data
R/W
McASP1
256
ROM Page2
256K Bytes
6 Serializers
32
Program
I/O
INT
Fetch
Program/Data
ROM Page3
32
McASP2
CELL ARRAY
256
2 DQ0
256K Bytes
2 Serializers
BANK #0
32
+ DIT
3 DQ1
5 DQ2
Program
CSP
32
32
32
SPI1
256
Cache
6 DQ3
32K Bytes
PMP DMP
32
SPI0
8 DQ4
32
32
9 DQ5
32
I2C0
11 DQ6
High-performance
32
Crossbar Switch
32
I2C1
12 DQ7
REFRESH
DQ
COUNTER
BUFFER
39 DQ8
32
32
32
32
32
RTI
40 DQ9
42 DQ10
I/O
Interrupts
MAX0
CONTROL
MAX1
Events
32
UHPI
43 DQ11
Out
In
EMIF
32
45 DQ12
PLL
dMAX
46 DQ13
48 DQ14
Peripheral Interrupt and DMA Events
49 DQ15
CELL ARRAY
BANK #1
14 LDQM
36 UDQM
COLUMN DECODER
COLUMN DECODER
CELL ARRAY
CELL ARRAY
BANK #0
BANK #1
SENSE AMPLIFIER
SENSE AMPLIFIER
DQ0
DATA CONTROL
DQ
CIRCUIT
BUFFER
DQ15
UDQM
LDQM
COLUMN DECODER
COLUMN DECODER
CELL ARRAY
CELL ARRAY
BANK #2
BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
159
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