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R[5:0]
G[5:0]
B[5:0]
RGB
CAPTURE
HSYNC
VSYNC
DCLK
Clock
Manager
PLL
Display Interface
SCLK
SDI
SIO
SDO
(HOST)
SCS
SCLEG[1:0]
ECLK
EDI
SIO
(EEPROM)
EDO
ECS
Noise
NRESET
Cancel
TEST0
TEST1
TEST
Circuit
TEST2
TEST3
CONFIDENTIAL
table
(P)
S
1-4
E
expand
L
table
(N)
Phase
Adjustment
Timing
Generator
Control
Power Block
Register
CR clock
Divider
CR
OCS
PowerOn
Reset
Reference
Voltage
6 – 33
8bit
A
Level
DAC
M
Shift
(RGBx4)
P
Pri
DAC
SEL
Level
Shift
Level
Shift
Booster
(x-1)
Booster
(x2)
Pre
Booster
5.1V
Regulator
4.9V
Regulator
1.8V
Regulator
802SH
AVOUT1_*
AVOUT2_*
AVOUT3_*
AVOUT4_*
(* :R,G, B)
PVOPL
PVOPH
PVONL
PVONH
PVOUT
COM
SCK
SCKB
SSPB
PCTL
GCK
GOE
GSPB
LR
UD
INIT
EXT1
EXT2
STATUS0
STATUS1
VEE_OUT
VDD_OUT
VIN
VDC2
VIN2
V51_OUT
V49_OUT
V18_OUT
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