SOYO SY-7VDA User Manual page 74

BIOS Setup Utility
CPU & PCI Bus Control
CPU to PCI
Write Buffer
PCI Master 0
WS Write
PCI Delay
Transaction
Setting Description
Disabled When this field is Enabled, writes
from the CPU to the PCI bus are
Enabled
buffered, to compensate for the
speed differences between the CPU
and the PCI bus. When Disabled,
the writes are not buffered and the
CPU must wait until the write is
complete before starting another
write cycle.
Disabled
Enabled When Enabled, writes to the PCI
bus are executed with zero wait
states.
Disabled The chipset has an embedded 32-bit
Enabled posted write buffer to support delay
transactions cycles. Select Enabled
to support compliance with PCI
specification version 2.1.
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SY-7VDA
Note
Default
Default
Default