SOYO SY-7VDA User Manual page 16

Motherboard Description SY-7VDA
correction and multi-bit detection) or EC (error checking) capability
separately selectable on a bank-by-bank basis. The DRAM controller can
run either synchronous or pseudo-synchronous mode with the host CPU
bus frequency (66 / 100 / 133 MHz).
The VT8633 Host system controller also supports full AGP v2.0 capability
for maximum bus utilization including 2x and 4x mode transfers, SBA
(SideBand Addressing), Flush/Fence commands, and pipelined grants. An
eight level request queue plus a four level post-write request queue with
thirty-two and sixteen quadwords of read and write data FIFO's
respectively are included for deep pipelined and split AGP transactions. A
single-level GART TLB with 16 full associative entries and flexible CPU /
AGP / PCI remapping control is also provided for operation under
protected mode operating environments. Both Windows-95 VXD and
Windows-98 / NT5 miniport drivers are supported for interoperability with
major AGP-based 3D and DVD-capable multimedia accelerators.
The VT8633 Host system controller supports two 32-bit 3.3 system buses
(one AGP and one V-Link) that are synchronous / pseudo-synchronous to
the CPU bus. The chip also contains a built-in bus-to-bus bridge to allow
simultaneous concurrent operations on each bus. Five levels (doublewords)
of post write buffers are included to allow for concurrent CPU and V-Link
operation. For V-Link Host operation, forty-eight levels (doublewords) of
post write buffers and sixteen levels (doublewords) of prefetch buffers are
included for concurrent V-Link bus and DRAM / cache accesses. When
combined the V-Link Host/Client controllers, it realizes a complete PCI
sub-system and supports enhanced PCI bus commands such as Memory-
Read-Line, Memory-Read-Multiple and Memory-Write-Invalid commands
to minimize snoop overhead. In addition, advanced features are supported
such as snoop ahead, snoop filtering, L1 write-back forward to PCI master,
and L1 write-back merged with PCI post write buffers to minimize PCI
master read latency and DRAM utilization. Delay transaction and read
caching mechanisms are also implemented for further improvement of
overall system performance.
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