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BIOS Setup Utility
DRAM Clock/Drive Control
DRAM Clock
/Driver Control
DRAM Timing
SDRAM Cycle
Length
Bank Interleave
DRAM Command
Rate
Setting
By SPD
HCLK-33M
HCLK+33M
By SPD
Manual
2.5
2
Disabled
2 Bank
4 Bank
2T Command
1T Command
Description
This item allows you to
control the DRAM speed.
If enable the DRAM will auto
detect the DRAM timing.
When synchronous DRAM is
installed, the number of clock
cycles of CAS latency
depends on the DRAM
timing. Do not reset this field
from the default value
specified by the system
designer.
Increase DRAM performance.
Increase DRAM performance.
66
SY-7VDA
Note
Default
Default
Default
Default
Default
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