Pll Frequency Synthesizer (Main); Master Reference Oscillator Circuit; 3Rd Local Oscillator Circuit; 2Nd Local Oscillator Circuit - Yaesu Mark-V FT-1000MP Field Technical Supplement

Circuit Description
power control, VR3003 (for setting transmission output, etc., on
the panel), and is then applied to op-amp IC Q3026-1
(M5218AFP).
The reflected voltage is added with a DC control voltage which
passes through VR3008, and is then applied to op-amp IC Q3026-
2. During high SWR conditions (SWR 3:1 or more), transmitter
output is reduced and a "High SWR" warning appears, thus pro-
tecting the PA Unit for potential damage.
The op-amp output passes through D3009 (1SS184) where
the forward and reflected output from the op-amp are mixed and
fed to the ALC amplifier, which contains a time-constant circuit.
The ALC amplifier amplifies the forward and reflected-wave
output via transistor Q3025 (2SC2812). This output then passes
through a fast-attack, slow-delay RC time-constant circuit consist-
ing of R3083/R3087 and C3069/C3157 for input to the Tx signal
control circuit via connector J3015 and J2004 on the IF Unit.
The TX control circuit adjusts the IF amplifier gain via gate 2
of FET Q2036 of the 8.215 MHz IF amplifier circuit to prevent
the Tx output from exceeding the preset level.
Keying Circuit
When the onboard electronic keyer is used in the CW mode,
the bias of Q1001, 2nd mixer FETs Q2033/Q2038, and 3rd mixer
D1001 is controlled via NAND gate IC Q1006 (µPD4011BG) to
generate CW.
To limit key clicks, the waveform is optimized by time-con-
stant circuits, such as D1002 (BAS316), R1016, and C1018 of
the bias control circuit.

PLL Frequency Synthesizer (Main)

The PLL Frequency Synthesizer consists mainly of a master
reference oscillator circuit, 2nd local oscillator circuit, 3rd local
oscillator circuit, DDS-PLL/DDS-SUB/DDS-CAR units which
digitally synthesize carrier outputs, and a PLL circuit which con-
tains a voltage controlled oscillator (VCO).

Master Reference Oscillator Circuit

The master reference oscillator uses a TCXO (oscillation fre-
quency: 10.48576 MHz) on the REF Unit.
The reference oscillator signal passes through a low-pass filter
composed of C4715/C4716, and L4702. It is then fedto the LO-
CAL Unit via J4703, and also to the RX2, AF, and DSP-D Unit as
the reference oscillation signal.
DDS-CAR Unit/DDS-PLL Unit/DDS-SUB Unit
DDS ICs Q3601 (TC23SC030AF), Q4502 (FQ7928), and
Q4603 (TC23SC030AF) of the DDS (Direct Digital Synthesizer)
Units each contain a shift register, selector, phase accumulator,
and ROM.
The reference oscillation frequency (10.48576 MHz) that is de-
livered to each of the DDS Units is applied to each DDS IC after
amplification by transistors Q3603/Q4503/Q4601 (all 2SC2812).
4-4
The DDS outputs contain digital amplitude data correspond-
ing to serial frequency data from CPU IC Q5008 of the CNTL
Unit. The digital amplitude data is D/A-converted by ladder resis-
tors RB3601/RB4501/RB4601 and passes through buffer ampli-
fier Q3602, Q4501, Q4602 (all 2SC2812) and a Chebychev LPF
to generate a sine wave. The DDS frequency range is 453.5 ~ 466.74
kHz (cf = 455.0 kHz) for the CAR-DDS, 373.08 ~ 291.16 kHz for
the DDS-PLL, and 907.88 kHz ±620 Hz for the DDS-SUB.

3rd Local Oscillator Circuit

The 3rd L.O. circuit generates a 1.81576 MHz signal by dou-
bling the 907.88 kHz output from the SUB-DDS Unit on the LO-
CAL Unit using a circuit composed of Q4036 (2SC2812), T4010,
capacitors C4163, C4164, C4170, and coil L4038. The doubled
signal is sent to mixer Q4027 (µPC1037).
At the mixer, the 1.81576 MHz input signal is mixed with the
10.48576 MHz reference oscillation signal. The mixer output is
stripped of unwanted frequency components by T4009 and mono-
lithic filter XF4001 to generate the 8.67 MHz 3rd L.O. signal.
This signal is amplified by Q4029 (2SC2812) and T4008 and
passes through buffer amplifier Q4017 (2SC2812) and a LPF com-
posed of capacitors C4098, C4099, C4172, and coil L4022 for
input to the IF Unit via connector J4003.

2nd Local Oscillator Circuit

The 2nd L.O. circuit is a Hartley-type overtone oscillator cir-
cuit (frequency: 62.24 MHz) composed of FET Q4003
(2SK210GR), T4001, and X4001 on the LOCAL Unit. The sig-
nal then passes through amplifier Q4012 (2SC2714Y), T4006,
T4007, and C4043, for input to the IF Unit via connector J4002.
1st Local Oscillator Circuit
VCO output is buffer-amplified by Q4004 and Q4005 (both
2SC2714Y) and passes through a LPF composed of coils L4003/
L4004 and capacitors C4028, C4029, and C4033-C4035. It is then
fed to the Tx/Rx frequency mixer circuitry of the RF Unit via con-
nector J4001.
PLL Circuit
The PLL circuit is a frequency mixing type composed of a VCO,
mixer, PLL IC, and loop filter.
The VCO consists of four circuits (VCO1, VCO2, VCO3, and
VCO4), with a frequency range of 70.555 ~ 100.455 MHz divided
into four bands, allocated to the four VCO circuits. The range of
VCO1 is further divided by a circuit which shifts the oscillation
frequency. VCO1-VCO4 consist mainly of FETs Q4009, Q4016,
Q4023, and Q4032 (all 2SK210BL), diodes D4001, D4002,
D4004, D4005, D4007, D4008, D4010, and D4011 (all
HVU306A), trimmer capacitors TC4001-TC4004, and coils
L4013, L4020, L4029, and L4035.
The VCO switching signal from connector J4004 is used to
drive switching transistors Q4013, Q4021, Q4026, and Q4037
(all 2SC4047) to switch the source terminal of the oscillator FET.