Sharp CD-DVD500 Service Manual page 74

CD-DVD500
IC505 RH-iX0454AWZZ: 6-Ch Code IC (AK4527BVQ) (1/2)
Pin No.
Terminal Name
1 SDOS
2 I2C
3 SMUTE
4 BICK
5 LRCK
6 SDTI1
7 SDTI2
8 SDTI3
9 SDTO
10 DAUX
11 DFS
12* N.C.
13 DZFE
14 TVDD
15 DVDD
16 DVSS
17 PDN
18 TST
19* N.C.
20 ADIF
21 CAD1
22 CAD0
23 LOUT3
24 ROUT3
25 LOUT2
26 ROUT2
27 LOUT1
28 ROUT1
29 LIN-
30 LIN+
31 RIN-
32 RIN+
33* DZF2
OVF
34 VCOM
35 VREFH
36 AVDD
37 AVSS
38* DZF1
39 MCLK
40 P/S
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Input/Output
Input SDTO source select pin. (Note 1)
"L": internal ADC output, "H": I2C DAUX input
Input Serial control mode select pin. "L": 3-wire serial, "H": I2C bus
Input Software mute pin. (Note 1)
Software mute is started with "H" and canceled with "L".
Input Audio serial data clock pin.
Input Input channel clock pin.
Input DAC 1 audio serial data input pin.
Input DAC 2 audio serial data input pin.
Input DAC 3 audio serial data input pin.
Output Audio serial data output pin.
Input Auxiliary audio serial data input pin.
Input Double-speed sampling mode pin. (Note 1)
"L": normal speed, "H": double speed
— —
Input Zero input detection function enable pin.
"L": mode 7 (disable) in parallel mode, selectable with DZFM 2-0 bit in serial mode.
"H": mode 0 (output from DZF1 with AND of 6 ch)
Input Power supply pin for output buffer, 2.7 V - 5.5 V.
Input Digital power supply pin, 4.5 V - 5.5 V.
— Digital ground pin, 0 V.
Input Power down & reset pin. When this pin is switched to "L", it enters the power down state
and the register is initialized. Reset it with the PDN pin if P/S and CAD 0-1 are changed.
Input Test pin. Connect it to DVSS.
— —
Input Analog input type select pin. "H": differential input, "L": single end input
Input Chip address 1 pin.
Input Chip address 0 pin.
Output DAC3 L channel analog output pin.
Output DAC3 R channel analog output pin.
Output DAC2 L channel analog output pin.
Output DAC2 R channel analog output pin.
Output DAC1 L channel analog output pin.
Output DAC1 R channel analog output pin.
Input L channel analog inversion input pin.
Input L channel analog non-inversion pin.
Input R channel analog inversion input pin.
Input R channel analog non-inversion pin.
Output Zero input detection 2 pin. (Note 2)
If the group 2 input data has been "0" for 8,192 consecutive times or the RSTN bit is "0", it
changes to "H".
Output Analog input overflow detection pin. (Note 3)
It changes to "H" when the analog input to Lch or Rch overflows.
Output Common voltage output pin, AVDD/2
Mount a capacitor of large capacity (approx. 2.2 µF) to remove power source noise.
Input Reference voltage input pin, AVDD.
Input Analog power supply pin, 4.5 V - 5.5 V.
— Analog ground pin, 0 V.
Output Zero input detection 1 pin. (Note 2)
If the group 1 input data has been "0" for 8,192 consecutive times or the RSTN bit is "0", it
changes to "H".
Input Master clock input pin.
Input Parallel/serial select pin.
"L": serial control mode, "H": parallel control mode
Function
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