Model 4 Theory Of Operation; Introduction; Cpu And Timing; Buffering - Radio Shack TRS-80 Model 4 Technical Reference Manual

3.1 Model 4 Theory of Operation

3.1.1

Introduction

The TRS-80 Model 4 Microcomputer is a self-contained
desktop microcomputer designed not only to be
completely software compatible with the TRS-80 Model
Ill, but to provide many enhancements and features.
System distinctions which enable the Model 4 to be
Model Ill compatible include: a Z80 CPU capable of
running at a 4 MHz clock rate, BASIC operating system
in ROM (14K), memory-mapped keyboard, 64-character
by 16-line memory-mapped video display, up to 128K
Random Access Memory, cassette circuitry able to
operate at 500 or 1500 baud, and the ability to accept a
variety of options. These options include: one to four 5-
1/4 inch double density floppy disk drives, one to four
five megabyte hard disk drives, an RS-232 Serial
Communications Interface, and a 640 by 240 pixel high
resolution graphics board.
3.1.2

CPU and Timing

The central processing
microcomputer is the Z80-A microprocessor
running at either a two (2.02752) or four (4 .05504) MHz
clock rate. The main CPU timing comes from the 20
MHz (20.2752 MHz) crystal-controlled oscillator, Y1 and
01. There is an additional 12 MHz (12.672 MHz)
oscillator, Y2 and 02, which is necessary for the 80 by
24 mode of video operation. The oscillator outputs are
sent to two Programmable Array Logic (PAL) circuits, U3
and U4, for frequency division and routing of appropriate
timing signals.
PAL U3 divides the 20 MHz signal by five for 4 MHz
CPU operation, by ten for a 2 MHz rate, and slows the 4
MHz clock for the Ml Cycle (See Figure 3-3). U3 also
divides the master clock by four to obtain a 5 MHz clock
to be sent to the RS-232 option connector as a reference
for the baud rate generator. PAL U4 selects an
appropriate 10 MHz or 12 MHz clock for the video shift
clock, and using divider US provides additional timing
signals to the video display circuitry (See Fig. 3-4).
Hex latch U18 is clocked from the 20 MHz clock, and is
used to provide MUX and CAS timing for the dynamic
memory circuits. Also, with additional gates from U16,
Port Addr. (Hex)
FC - FF
F8 - FB
(1) F4 - F7
(1) F3
(1) F2
(1) F1
CPU CIRCUIT BOARD
unit of the Model
capable of
-
Read Function
Cassette In, Mode Read
Read Printer Status
-reserved-
FDC Data Reg.
FDC Sector Reg.
FDC Track Reg.
U19, U20, U31, and U32, this chip provides the wait cir-
cuitry necessary to prevent the CPU from accessing
video RAM during the active portion of the display. This
is done by latching the data for the video RAM and
simultaneously forcing the Z80 CPU into a "WAIT" state
and is necessary to eliminate undesirable "hashing" of
the video display (See Fig. 3-4).
3.1.3

Buffering

Low level signals from and to the CPU need to be
buffered, or current amplified in order to drive many
other circuits. The 16 address lines are buffered by U55
and U56, which are unidirectional buffers that are
permanently enabled. The eight data lines are buffered
by U71. Since data must flow both to and from the CPU,
U71 is a bi-directional buffer which can go into a three-
state condition when not in use. Both direction and
enable controls come from the address decoding
4 section.
The clock signal to the CPU (from PAL U3) is buffered
by active pullup circuit 03 RESET and WAIT inputs to
the CPU are buffered by U17 and U46. Control outputs
from the Z80 (M1*, RD*, WR*, MREQ*, and IORQ*) are
sent to PAL U58, which combines these into other
appropriate control signals consistent with Model 4's
architecture. Other than MREQ*, which is buffered by
part of U38, the raw control signals go to no other
components, and hence require no additional buffering.
3.1.4

Address Decoding

The address decoding section is divided into two sub-
sections: Port address decoding and Memory address
decoding.
In port address decoding, low order address lines (some
combined through a portion of U32) are sent to the
address and enable inputs of U48, U49, and USO. U48
is also enabled by the IN~ signal, which means that is
decodes port input signals, while U49 decodes port
output signals. A table of the resulting port map is shown
below:
15
Write Function
Cassette Out, resets
cassette data latch
Output to Printer
Drive Select latch
FDC Data Reg.
FDC Sector Reg.
FDC Track Reg.