No action arising out of any claimed breach of this Warranty or transactions under this Warranty may be brought more than two (2) years after the cause of action has accrued or more than four (4) years after the date of the Radio Shack sales document for the Equipment or Software, whichever first occurs.
TRS-80 Model 4 operation. Radio Shack will not be liable for any damage caused, or alleged to be caused, by the customer or any other person using this technical manual to repair, modify, or alter the TRS-80 Model 4 Computer in any manner.
TABLE OF CONTENTS Part 1 / Hardware SECTION I Introduction.............................1 SYSTEM OVERVIEW ........................3 BLOCK DIAGRAM..........................3 JUMPER OPTIONS..........................5 SECTION II Disassembly / Assembly........................7 Disassembly .............................9 2.1.1 Case ..............................9 2.1.2 CPU Board............................9 2.1.3 FDC Board (optional)........................9 2.1.4 RS-232 Board (optional) ........................9 2.1.5 Main Power Supplies ........................9 2.1.6 Disk Drives (optional)........................9...
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4.1.2 Nonmaskable Interrupt Logic......................55 4.1.3 Drive Select Latch and Motor On Logic ..................55 4.1.4 Wait State Generation and WAITIMOUT Logic ................56 4.1.5 Clock Generation Logic ......................... 56 4.1.6 Disk Bus Selector Logic ......................... 56 4.1.7 Read/Write Data Pulse Shaping Logic ..................56 4.1.8 Disk Bus Output Drivers ........................
LIST OF FIGURES Fig. No. Description Page No. TRS-80 Model 4 Interconnection Diagram Model 4 Block Diagram RAM Memory Timing of U3 & CPU Timing of U4 CPU Video Access Timing I/O Bus Timing Diagram Write Precompensation Timing...
The Radio Shack TRS-80 Model 4 Microcomputer is an enhanced version of Radio Shack’s popular TRS-80 Model Ill Microcomputer. The TRS-80 Model 4 is software compatible with the Model Ill so that owners of either system can take advantage of the large number of programs available.
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FIGURE 1-1. TRS-80 MODEL 4 INTERCONNECTION DIAGRAM...
DISASSEMBLY / ASSEMBLY 2.1.4 RS-232 Board (optional) 2.1 Disassembly NOTE: The CPU Board must be removed before 2.1.1 Case removing the RS-232 Board. 1. Remove all cables from the bottom and rear of 1. Be sure to remove all cables connecting the RS- the Computer.
2. Remove the four screws and washers (two on WARNING each side) which connect the Drive to the Disk There may be a high voltage charge on the high Mounting Bracket. Remove the RFI shield which voltage anode. To discharge, connect one end of a covers the top drive.
2.2.6 Disk Drive Power Supply (optional) 2.2 Assembly 1. Before installing the Power Supply be sure that 2.2.1 RS-232 Board (optional) the bottom Disk Drive is mounted in place and 1. Install the PC Board using #6 x 1/4” screws. If the Disk Shield is in position on the Disk applicable, press the PC Board onto the plastic Mounting Bracket.
3.1 Model 4 Theory of Operation 3.1.1 Introduction The TRS-80 Model 4 Microcomputer is a self-contained U19, U20, U31, and U32, this chip provides the wait cir- desktop microcomputer designed not only to be cuitry necessary to prevent the CPU from accessing completely software compatible with the TRS-80 Model video RAM during the active portion of the display.
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FDC Status Reg. FDC Command Reg. EC - EF Resets RTC Int. Mode Output latch Rcvr Holding Reg. Xmit Holding Reg. UART Status Reg. UART/Modem control -reserved- Baud Rate Register Modem Status Master Reset/Enable UART control reg. E4 - E7 Read NMI Status Write NMI Mask reg.
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Following is a Bit Map of the appropriate ports in the Model 4. Note that this is an “internal” bit map only. For bit maps of the optional devices, refer to the appropriate section of the desired manual. Model 4 Port Bit Map Port FC-FF Cass...
3C00 - 3FFF Video RAM 4000 - 7FFF RAM (16K) End of one 32K Bank 8000 - FFFF RAM (32K) Second 32K Bank Memory Map III 0000 - 7FFF RAM (32K) End of One 32K Bank RAM (29K) Second 32K Bank 8000 - F3FF Keyboard F400 - F7FF...
3.1.9 Real Time Clock 3.1.11 Printer Circuitry The Real Time Clock circuit in the Model 4 provides a The printer status lines are read by the CPU by 30 Hz (in the 2 MHz CPU Mode) or 60 Hz (in the 4 enabling buffer U67.
See Model 4 Port Bit assignment for port 0FE, 0EC, 3.2 Model 4 I/O Bus and 0E0 on pages 28 and 29. The Model 4 Bus is designed to allow easy and The Model 4 CPU board is fully protected from convenient interfacing of I/O devices to the Model 4.
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Input or Output Cycles ∞ ∞ ∞ ∞ Inserted by Z80 CPU Input or Output Cycles with Wait States. ∞ ∞ ∞ ∞ Inserted by Z80 CPU †Coincident with IORQ* only on INPUT cycle FIGURE 3-6. I/O BUS TIMING DIAGRAM...
3.3 Model 4 Port Bits Name: WRNMIMASKREG* Name: RDINTSTATUS* Port Address: 0E4H Port Address: 0E0H Access: WRITE ONLY Access: READ ONLY Bit 7 = ENINTRO; 0 disables Disk INTRQ from NOTE: A 0 indicates the device is interrupting. generating an NMI. 1 enables above.
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Name: WRINTMASKREG* Name: DRVSEL* Port Address: 0E0H Port Address: 0F4H Access: WRITE ONLY Access: WRITE ONLY Bit 7 = Undefined Bit 7 = FM*/MFM; 0 selects single density, 1 selects double density. Bit 6 = ENERRORINT; 1 enables RS-232 interrupts on parity error, framing error, or data overrun Bit 6 = WSGEN;...
Parts List, CPU PCB 8858090 Model 4 64K, Single or Double Drive Catalog Number 26-1068 or 26-1069 Item Description Mfgr’s Part No. Cap, 100 pfd 50V C. Disk (C1,99,101,103) 8301104 Cap, 10 MFD 35V ELEC. RAD (C2-4) 8326103 Cap, 0.1MFD 50V MONO AXIAL 8374104 (C5,11-18,23,26-29,31,33-37,39-41,43, 47-55,57-65,67,69,71,73,75,77,79,81,83,...
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Parts List, CPU PCB 8858090 Model 4 64K, Single or Double Drive Catalog Number 26-1068 or 26-1069 Item Description Mfgr’s Part No. IC, 74LS166 Shift Register (Ull) 8020166 IC, 74LS51 AND OR Invert (U12,20) 8020051 IC, 74LS00 Quad 2-In NAND (U13,14) 8020000 IC, LM339 Comparator (U15) 8050339...
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Parts List, CPU PCB 8858090 Model 4 64K, Single or Double Drive Catalog Number 26-1068 or 26-1069 Item Description Mfgr’s Part No. Res, 10K ohm, 5% 1/4w (R5,9,14,16) 8207310 Res, 3.6K ohm, 5% 1/4W (R6) 8207236 Res, 91 ohm, 5% (R7) 8207091 Res, 4.7K ohm, 5% 1/4W 8207247...
4.1 Model 4 FDC PCB #8858060 interrupt to the CPU. The NMI-interrupt conditions are The TRS-80 Model 4 Floppy Disk interface Board is programmed by doing an OUT instruction to port E4H an optional board which if incorporated provides a with the appropriate bits set.
4.1.4 Wait State Generation and WAITIMOUT Drive 2 or Drive 3 is selected, U17 pin 1will go low Logic indicating that an external drive is selected. One half of U10 (a five input NOR gate) is used to detect when As previously mentioned, a wait state to the CPU can one of the four drives is selected.
02 is used as the write data pulse on nominal 4.1.11 Adjustments and Jumper Options (EARLY = 0 LATE = 0). 01 is used for the early, and The Data Separator must be adjusted with the 1793 03 is used for the late. The leading edge of 04 resets in an idle condition (no command currently in the STB line in anticipation of the next write data operation).
PARTS LIST, FLOPPY DISK INTERFACE PC BOARD #8858060 MANUFACTURER’S RADIO SHACK SYMBOL DESCRIPTION PART NUMBER PART NUMBER CAPACITORS 0.lµF, 50V, monolithic, radial 838-4104 ACC104QJAP 0.lµF, 50V, monolithic, radial 838-4104 ACC104QJAP 0.lµF, 50V, monolithic, radial 838-4104 ACC104QJAP 0.lµF, 50V, monolithic, radial...
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PARTS LIST, FLOPPY DISK INTERFACE PC BOARD #8858060 MANUFACTURER’S RADIO SHACK SYMBOL DESCRIPTION PART NUMBER PART NUMBER INTEGRATED CIRCUITS (cont’d) 74LS174, Quad “D” Flip-Flop 802-0174 AMX3565 WD1793 850-9002 AXX3041 74LS38. NAND Buffer 802-0038 AMX4328 7416, Hex Inverter/Buffer 800-0016 ------- 74LS260, Dual NOR gate...
CPU to check the FDC board to determine the source 4.2 Model 4 FDC PCB #8858160 of the non-maskable interrupt. Data bit 7 indicates the The TRS-80 Model III/4 Floppy Disk Interface Board status of FDC interrupt request (0 = true, 1 = false). is an optional board which, if incorporated, provides a Data bit 6 indicates the status of Motor Time Out (0 standard 5-1/4”...
perform this function. INTQ, DRQ, RESET, and are selected, otherwise the internal inputs are WAITIMOUT are the inputs to the NOR gate. If any selected. This control signal EXTSEL* is generated one of these inputs is active (logic high), the output of from the outputs of the Drive Select Latch.
4.2.9 Clock and Read Data Recovery Logic 4.2.10 Floppy Disk Controller Chip The Clock and Read Data Recovery Logic is The 1793 is an MOS LSI device which performs the comprised of one chip, the FDC9216. The FDC9216 functions of a floppy disk formatter/controller in a is a Floppy Disk Data Separator (FDDS) which single chip implementation.
Parts List, Model 4 Computer, #26-1067/8/9 Item Description Mfgr’s PN RS Part No Case Top 8719104 Base 8719265 Feet, Case 8590098 Keyboard 8790524 Keyboard Bezel 8719164 Bracket, Disk Mounting (LH) 8719106 Bracket, Disk Mounting (RH) 8719105 Shield, Disk (RH side) 8729093 Power Supply Assy.(on 26-1067) 8790021...
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Parts List, Model 4 Computer, #26-1067/8/9 Item Description Mfgr’s PN RS Part No Cable, Ground 8709193 Ground, Main 8709161 Clip, Tinnerman 8559031 Cable Assembly, CRT 8709369 for Models 26-1068/1069 for Model 26-1067 8709286 Clip, Tinnerman ------- Bracket, Support 8729055 Strain Relief, Power Cord 8559014 FDC PCB Assembly 8858060 or...
RS-232C CIRCUIT BOARD 9.1 RS-232C Technical Description The RS-232C option board for the Model 4 computer supports asynchronous serial transmissions and conforms to the EIA RS-232C standards at the input - output interface (P1). The heart of the board is the TR1602 Asynchronous Receiver/Transmitter.
The RS-232C board is a port mapped device and the 9.2 Pinout Listing ports used are E8 to EB. Following is a description of The following list is a pinout description of the DB-25 each port on both input and output. connector (P1).
9.3 Port and Bit Assignments PORT OUTPUT: MASTER RESET INPUT: MODEM STATUS REGISTER An output to this port (and data), performs a master reset to the UART and enables the control register load enable bit. The following table details the bit definitions for an input from port E8H. DATA BIT FUNCTION Clear To Send, Pin 5 DB-25...
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PORT EAH OUTPUT BITS WITH UART CONTROL REGISTER DISABLED DATA BIT FUNCTION Not Used Not Used Secondary unassigned, Pin 18 DB-25 Secondary Transmit Data, Pin 14 DB-25 Secondary Request To Send, Pin 19 DB-25 Break 0 = disable Transmit Data (continuous space) Data Terminal Ready, Pin 20 DB-25 Request To Send, Pin 4 DB-25 PORT EAH INPUT BITS...
PARTS LIST RS-232C PC BOARD MANUFACTURER’S RADIO SHACK SYMBOL DESCRIPTION PART NUMBER PART NUMBER CAPACITORS l0µF, 16V, radial (optional) 832-6101 ACC106QDAP l0µF, 16V, radial (optional) 832-6101 ACC106QDAP 0.1µF, 50V, monolithic, radial 838-4104 ACC104QJAP 0.1µF, 50V, monolithic, radial 838-4104 ACC104QJAP 0.1µF, 50V, monolithic, radial...