Theory Of Operation - Radio Shack TRS-80 Reference Handbook

heory
System Clock
The System Clock is shown on Sheet 2 of the
fold-out Schematics at the back of this book.
Y1 is a 10.6445 MHz, fundamental-cut crystal.
It is in a series resonant circuit consisting of two
inverters. Z42, pins 1 and 2. and 3 and 4, form
two inverting amplifiers. Feedback between the
inverters is supplied by C43, a 47 pF capacitor.
R46 and R52 force the inverters used in the
oscillator to operate in their linear region.
The waveform at pin 5 of Z42 will resemble a
sine wave at 10.6445 MHz. The oscillator should
not be measured at this point, however, due to
the loading effects test equipment would have at
this node. Z42, pin 6, is the output of the oscil-
lator buffer. Clock measurements may be made
at this point. The output of the buffer is applied
to three main sections: the CPU timing circuit,
the video divider chain, and the video processing
circuit.
CPU Timing
The
Z80
microprocessor needs a single phase
clock source for operation. The 10 MHz signal
from System Clock is applied to
Z56,
a standard
ripple counter, which is used as a divide-by-6
counter. The resulting signal at
Z56,
pin 8, is a
little over 1.774
MHz.
The signal is applied to
the input of buffer Z72, pin 12. Pin 11 of Z72
is attached to pin 6 of the
Z80
microprocessor.
R64 pulls up pin 11 of Z72, and insures a rapid-
ly increasing rise time for the clock signal.
Notice that pin 15 of Z72 is tied to ground.
Since pin 15 is the enable input to th is part of
Z72. pins 12 and 11 will always be active.
14
f peration
Notice also pins 7 and 6 of
Z56.
These two pins
enable the clear function for the counter. When
one or both of these pins is low, the counter
operates normally. When high, the input forces
the counter into its clear or reset state.
Z42, pins 9 and 8, are used to disable counter
Z56 during automatic testing at the factory.
R67 pulls Z42's input to Vee, which causes
pin
8
to stay at a logical low. During testing, pin
9 of Z42 may be pulled low, making pin 8 high,
which disables and clears
Z56.
NOTE: You might also find early Board ver-
sions ("AI! Boards for example) where pins 6
and 7 of Z56 are tied directly to ground.
Power-Up-Clear and System Reset
As mentioned in the Block Diagram discussion,
upon power-on the CPU accesses a known
address in the ROM for instructions. The circuit-
ry which causes the starting address output is
shown just below the microprocessor clock
divider.
Z53 is a 2-input, quad NAND gate. (Note that
Z53 is drawn as an inverted input OR gate.)
When power is first applied to the system, C42
is at (i'volts. R47 is tied to Vee and starts charg-
ing
C4
at a known rate. While
C4
is charging,
and before the voltage exceeds the logical 1 level
for
Z53,
pin 11 outputs a high. This high is in-
verted by Z52, pins 11 and 10, and a low is
applied to pin 26 of Z40.
A low at this input forces the microprocessor to
output the starting address 0000 on its 16
address lines. When e42 charges up past about
1.4 volts,
Z53,
pin 11, goes low, which causes
Z52, pin 10, to go high. The CPU is now out of