Radio Shack TRS-80 Model 4 Technical Reference Manual page 39

Input or Output Cycles
∞ ∞ ∞ ∞
Inserted by Z80 CPU
Input or Output Cycles with Wait States.
∞ ∞ ∞ ∞
Inserted by Z80 CPU
†Coincident with IORQ* only on INPUT cycle
FIGURE 3-6. I/O BUS TIMING DIAGRAM
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