Theory Of Operation - Radio Shack TRS-80 Technical Manual

THEORY
OF OPERATION
System Clock
The
system clock
is
shown
on Sheet 2 of the fold-out
schematics
in
the
Schematic
Section.
Y1
is
a
10.6445
MHz,
fundamental
cut, crystal.
It
is
in a series
resonant
circuit
consisting of
two
inverters.
Z42,
pins
1
and
2,
and 3 and
4,
form two
inverting amplifiers.
Feedback between
the
inverters
is
supplied by C43,
a
47 pF
capacitor.
R46
and
R52
force the inverters
used
in
the oscillator to
operate
in
their linear region.
The waveform
at
pin 5 of
Z42
will
resemble
a sine
wave
at
10.6445
MHz. The
oscillator
should
riot
be measured
at this point,
however, due
to the loading
effects test
equipment would
have
at this
node.
Z42,
pin
6,
is
the
output of the
oscillator buffer.
Clock measurements
may
be
made
at this
point.
The
output
of the buffer
is
applied to three
main
sections:
the
CPU
timing
circuit,
the
video divider chain,
and
the
video processing
circuit.
CPU
Timing
The Z80
microprocessor needs
a
single
phase clock source
for.
operation.
The
10
MHz
signal
from
system clock
is
applied to
Z56,
a
standard
ripple
counter,
which
is
used
as a
divide-by-6 counter.
The
resulting signal at
Z56,
pin
8, is
a
little
over 1.774
MHz. The
signal
is
applied to the input of
buffer
Z72,
pin 12. Pin 11 of
Z72
is
attached
to pin
6
of
the
Z80
microprocessor.
R64
pulls
up
pin
11
of
Z72, and
insures
a
rapidly increasing
rise
time
for
the clock
signal.
Notice
that pin
15 of
Z72
is
tied
to ground. Since pin
15
is
the enable input to
this
part of
Z72,
pin
12 and
11 will
always be
active.
Notice
also
pins 7 and 6
of
Z56. These
two
pins enable the clear
function
for the counter.
When
one
or
both
of these pins
is
low, the counter operates
nor-
mally.
When
high,
the input forces the counter into
its
clear
or reset
state.
Z42,
pins
9 and
8,
are
used to
disable
counter
Z56
during automatic
testing at
the factory.
R67
pulls
Z42's input
to VrjC.
which
causes pin 8 to stay at a logical
low.
During
testing,
pin
9 of
Z42
may
be pulled low,
mak-
ing pin
8
high,
which
disables
and
clears
Z56.
You
might
also
find early
Board
levels
(A Boards
for
example) where
pins
6 and
7 of
Z56
are tied directly to
ground.
Power-Up-Clear and
System
Reset
A
low
at this
input
forces
the microprocessor to
output
the
starting address
0000 on
its
16 address
lines.
When C42
charges
up
past
about
1.4 volts,
Z53,
pin 11, goes low,
which
causes
Z52,
pin 10, to
go
high.
The
CPU
is
now
out
of
its
reset state,
and
will start
executing instructions
from
the
ROM,
starting at address
0000. Notice that the only
time
pin
26 of the
CPU
is
ever
low
is
a
few
milliseconds
after
power
is
applied.
Once C42
charges
up
past the logical
ONE
level,
pin
26
stays high until
C42
is
discharged
when
power
is
removed.
Why
is
Z53,
a
NAND
gate,
drawn
like
an
OR
gate?
Notice that
pin
1 1
is
high
only
when
either
of
the inputs
are low.
The
NOT
circles at
the input
immedi-
ately
tell
you
that
this
gate
is
looking
for
a signal
that
is
low
to cause an output that
is
high.
Had
the
gate
been drawn
"correctly",
then
it
would
not have been
so
obvious
that
the
output
is
active
when
high.
This "functional" type of
logical
symbolization
is
used throughout the schematics.
Directly
above
the power-up
circuit, there
is
a
similar
cir-
cuit.
S2
is
the
reset
switch located
on
the
right side
of the
Board.
Although
there
is
a
power-on-delay type
circuit
on
the input of
this
network,
it is
not used
as
such. Notice that
C57
is
smaller than C42. Hence,
in a
power-up
"race",
C57
would
charge
up
faster
than C42.
Assume
that
C57
is
charged. Also
assume
that pin 2 of
Z53
is
high.
This
means
that
Z53,
pin
3, will
be
low
and Z37,
pin
13, will
be high.
With
pin 17 of the
CPU
held
high,
everybody
is
happy.
If
S2
is
pressed,
C57
will
discharge through the switch.
The
resulting
low
is
applied to pin
1
of
Z53
and
pin
3
goes high.
Z37, pin
13,
is
then forced low.
A
low
at
pin
1
7 of the
CPU
forces the
microprocessor
to restart at address
0066.
When
S2
is
released,
R65
begins to charge
C57
until a logical
high
is
applied to pin
1
of
Z53. At
this time, pin
17 of the
CPU
goes
back
high
and
the
CPU
starts
executing instructions
from
address
0066
in
the
ROMs.
S2
is
used
to get the
microprocessor back on
the
right
road
when
it is
"lost".
This switch
forces the
CPU
toward
a
known
address to enable
it
to
get
on
the
right track.
An
example
of
a lost
CPU
would
be during
a
bad
cassette
load
attempt.
If
a
cassette
is
loading
and suddenly
there
is
missing information
on
the tape (caused by
dirt
or
age),
the
recorder
may
never stop.
S2 can then
be pressed,
which
directs
the
CPU
out of the cassette load routine and back
into
its
ready
mode.
As mentioned
in
the block
diagram
discussion,
upon power-
on
the
CPU
accesses
a
known
address
in
the
ROM
for
instructions.
The
circuitry
which
causes the starting
address
output
is
shown
just
below
the
microprocessor clock
divider.
Z53
is
a
2-input,
quad
NAND
gate.
(Note that
Z53
is
drawn
like
an inverted input
OR
gate.)
When
power
is
first
applied to the system,
C42
is
at
volts.
R47
is
tied to
Vcc
ar|
d
starts
charging
C4
at a
known
rate.
While
C4
is
charging,
and before the voltage exceeds the
logical
1
level
for
Z53,
pin 11
outputs
a
high.
This high
is
inverted
by
Z52,
pins
1 1
and
10,
and
a
low
is
applied to pin
26
of
Z40.
The
output
at pin
18 of
Z40
is
called
"Halt".
In
Level
I
BASIC,
this
output should
never be low.
It
goes
low only
when
a
software halt instruction
is
encountered by Z40.
In
theory,
this
instruction
is
not included
in
the
ROMs.
But
you might
find pin 18 held
low because
Z40
thought
it
was
told to
halt.
It
could be
due
to
some
data malfunction, or
the
CPU
is
lost
and
is
playing around with display data
instead of
ROM
data.
In a
case
like this,
S2
is
not
effective
in
bringing the
CPU
home,
because
Z53
is
latched up.
About
all
you
can
do
is
shut the
computer
down
and
try
again.