Aiwa XR-MK7 Service Manual page 47

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IC, LC74781M
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Pin Name I/O
VSS1 — GND connection terminal. (Digital ground terminal).
Xtal IN I External X'tal and capacitor for internal sync generator, or the external clock are
Xtal OUT O connected to this terminal. (2fsc or 4fsc).
Either the external clock input mode or the X'tal generator mode is selected by this
CTRL1 I
selector terminal. L: X'tal generator mode, H: External clock input.
Blank signal (character and the green ORed signal) is output from this terminal.
BLANK O (MODE 0: composite sync signal is output at H.) When reset (RST terminal = L), the
X'tal clock signal is output. (It is not output when reset by the reset command).
OSC IN I External coil and capacitor for the character output dot clock generator are connected
OSC OUT O to this terminal.
The character signal is output from this terminal. (MOD 0: when H, the external sync
signal identification signal is output from this terminal. This output signal tells whether
CHARA O the external sync signal is present or not. When external sync signal is present, H is
output.) When reset (RST terminal = L), the dot clock signal (LC oscillator) is output.
(It is not output when reset by the reset command).
Enable signal for the serial data input is input to this terminal. The serial data input is
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CS I
enabled at L. Pull-up resistor is built-in. (Hysteresis input).
Clock of the serial data input is input to this terminal. Pull-up resistor is built-in.
SCLK I
(Hysteresis input).
SIN I Serial data input terminal. Pull-up resistor is built-in. (Hysteresis input).
VDD2 — Power supply for the composite video signal level adjustment. (Analog power supply).
CV OUT O Composite video signal output terminal.
NC — Connected to GND or not connected.
CV IN I Composite video signal input terminal.
VDD1 — Power supply (+5V digital power supply).
Video signal for the internal sync separator circuit is input to this terminal. (When the
SYN IN I internal sync separator circuit is not used, the horizontal sync signal or composite sync
signal is input to this terminal).
SEP C — Internal sync separator circuit bias voltage monitoring terminal.
The composite sync output signal of the internal sync separator circuit is output from
O this terminal. (H: MOD 1. H: during internal sync mode. L: during external sync
SEP OUT
mode.) (When internal sync separator circuit is not used, the SYN IN input signal is
output from this terminal).
The output signal of the SEP OUT terminal is integrated so that the vertical sync signal
is input to this terminal. An integrator circuit must be connected between the SEP
SEP IN I
OUT terminal and this terminal. When this terminal is not used, it must be connected
to VDD1.
When selecting any of the NTSC or PAL or PAL-M or PAL-N system, the pin setting
has priority. When L, the NTSC system is selected after resetting. Selection of either
CTRL2 I
x ao
y
NTSC or PAL or PAL-M or PAL-N system by the command becomes effective. H:
i
PAL-M system.
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