Aiwa XR-MK7 Service Manual page 43

Compact disc stereo system
Table of Contents

Advertisement

QQ
3 7 63 1515 0
Pin No.
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
TE
L 13942296513
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
www
73
74
75
.
76
http://www.xiaoyu163.com
Pin Name
I/O
DA11
O
DA11 output when PSSL=1. GTOP output when PSSL=0.
DA10
O
DA10 output when PSSL=1. XUGF output when PSSL=0.
DA09
O
DA09 output when PSSL=1. XPLCK output when PSSL=0.
DA08
O
DA08 output when PSSL=1. GFS output when PSSL=0.
DA07
O
DA07 output when PSSL=1. RFCK output when PSSL=0.
DA06
O
DA06 output when PSSL=1. C2PO output when PSSL=0.
DA05
O
DA05 output when PSSL=1. XRAOF output when PSSL=0.
DA04
O
DA04 output when PSSL=1. MNT3 output when PSSL=0.
DA03
O
DA03 output when PSSL=1. MNT2 output when PSSL=0.
DA02
O
DA02 output when PSSL=1. MNT1 output when PSSL=0.
DA01
O
DA01 output when PSSL=1. MNT0 output when PSSL=0.
Aperture compensation control output.
APTR
O
This pin outputs a high signal when the right channel is used.
Aperture compensation control output.
APTL
O
This pin outputs a high signal when the left channel is used.
VSS
GND.
XTAI
I
Crystal oscillation circuit input.
XTAO
O
Crystal oscillation circuit output.
XTSL
I
Crystal selector input.
FSTT
O
2/3 frequency divider output for Pins 53 and 54.
FSOF
O
1/4 frequency divider output for Pins 53 and 54.
C16M
O
16.9344MHz output. (V16M output in CLV-W and CAV-W modes)
MD2
I
Digital-out on/off control. High: on; low: off
DOUT
O
Digital-out output.
Outputs a high signal when the playback disc has emphasis, and a low signal when
EMPH
O
there is no emphasis.
WFCK
I
WFCK (write frame clock) output.
SCOR
O
Outputs a high signal when either subcode sync S0 or S1 is detected.
SBSO
O
Sub P to W serial output.
EXCK
I
SBSO readout clock input.
SQSO
O
Sub Q 80-bit and PCM peak, level metter and internal status outputs.
SQCK
I
SQSO readout clock input.
MUTE
I
High: mute; low: release
SENS
SENS output to CPU.
XRST
I
System reset. Reset when low.
DATA
O
Serial data input from CPU.
XLAT
O
Latch input from CPU. Serial data is latched at the falling edge.
VDD
Power supply (5V).
x
ao
CLOK
O
Serial data transfer clock input from CPU.
y
SEIN
I
SENS input from SSP.
i
CNIN
I
Track jump count signal input.
http://www.xiaoyu163.com
8
Q Q
3
6 7
1 3
u163
.
63
2 9
9 4
2 8
Description
1 5
0 5
8
2 9
9 4
m
co
9 9
2 8
9 9

Hide quick links:

Advertisement

Table of Contents
loading

This manual is also suitable for:

Xr-mk7 hrXr-mk7 hc

Table of Contents