Advertisement
Q Q
3 7 6 3 1 5 1 5 0
CLOCK FLOW & WAVE FORM IN DIGITAL BLOCK
Clock Flow
1
INPUT
SELECTOR
DIR
A/D SELECTOR
IC111
IC107
IC104
LC89055W
74LVX157MTC
SN74HC
151APW
CKOUT(13)
(5)
(5)DIN2
BCK(14)
LRCK(15)
DATAD(16)
XIN(22)
12.287MHz
IC113
(7)
SG-8002
(13)
(3)
(10)
IC112
SN74LV4040APW
A/D CONVERTER
IC114
AK5353VS
T E
L
MCLK(17)
1 3 9 4 2 2 9 6 5 1 3
AIN
SCLK(18)
LRCK(19)
SDATA(21)
* fs is a sampling frequency of input digital signal.
e.g.: sampling frequency 48 kHz → fs=48 kHz
* 64fs and 256fs are 64 or 256 times the sampling frequency
respectively.
e.g.:sampling frequency 48 kHz
64fs:48kHz x 64 = 3.072MHz
256fs:48kHz x 256 = 12.288MHz
* The sampling frequency for analog input is fixed to 48kHz internally.
* (No.) indicates the pin number of individual IC.
* The arrow indicates the direction of signal flow. As the input terminal
pointed by the arrowhead and the output terminal by the opposite.
w w w
.
IC523
IC512
SN74LV4040APW
SN74LV86APW
SYNC
(11)
(9)
(3)
(7)
(10)
(13)
(10)
SN74LV00APW
IC511
256fs
64fs
fs
DATA
64fs
2
fs
(2)
(13)
(4)
(15)
(7)
TFS0
RFS0 RFS1 RCLK0 RCLK1
IC501
ADSP-21065L
TCLK0(8)
(4)RCLK0
TCLK1(19)
(15)RCLK1
TFS0(7)
(2)RFS0
TFS1(18)
(13)RFS1
DATA
(5)DR0A
DT0A(11)
(5)DR0A
DT0B(12)
(6)DR0B
DT1A(22)
(16)DR1A
DT1B(23)
(17)DR1B
1st DSP
DOLBY DIGITAL Decode
THX Filter Processing
DTS-ES Decode
EX/ES Matrices Processing
AL24 Processing
Sound Simulation
Bus-Management Processing
x
a o
y
i
http://www.xiaoyu163.com
8
3
D/A CONVERTER
AD1854K
256fs
(2)MCLK
64fs
(26)BCLK
fs
(25)LRCLK
(27)SDATA
AD1854K
(2)MCLK
(26)BCLK
(25)LRCLK
(27)SDATA
SUBWOOFERch
(18)
(8)
(19)
TFS1 TCLK0 TCLK1
IC502
ADSP-21065L
Q
Q
3
7
6
3
AD1854K
(2)MCLK
(26)BCLK
(25)LRCLK
(27)SDATA
DT0A(11)
DT0B(12)
SURROUNDch
DT1A(22)
DT1B(23)
2nd DSP
AD1854K
(2)MCLK
(26)BCLK
(25)LRCLK
(27)SDATA
SURROUND BACKch
u 1 6 3
.
2
4
9
9
8
Wave Form
IC301
FRONTch
IC303
CENTERch
IC305
1
5
1
5
0
8
9
2
4
IC307
m
c o
AVR-4802/AVC-A11SR
2
9
9
1
CH1: IC104 (5)
2
CH1: DATA
9
8
2
9
9
CH2: fs
CH3: 64fs
3
CH1: 64fs
CH2: fs
CH3: 256fs
CH4: FRONT DATA
9
Advertisement
