Sharp DV-NC55S Service Manual page 56

DV-NC55S/H
DV-NC60H
12-2. IC501 IX1689GE
Pin No. Symbol
45 DQ /A
15
25-18, 8-4 A -A
0 12
3-1, 48,
A -A
16, 17 13 18
29, 31, 33,
35, 38, 40, DQ -DQ
0
42, 44
30, 32, 34, 36,
DQ -DQ
39, 41, 43, 45
8
26 CE#
12 RP#
28 OE#
11 WR#
14 WP#
15 RY/BY#
47 BYTE#
13 Vpp
37 Vcc
27, 46 GND
9, 10 NC
FLASH MEMORY
Type
Byte selection address: When the device is in the x8 mode, the low or high order byte is
Input selected. It is not used in the x16 mode.
-1
(If BYTE# is high, DQ
Word selection address: Selection of one word of 16k byte block. These addresses are
Input
latched during data wiring operation.
Block selection address: Selection of 1/32 erase block. These addresses are latched
Input
during data writing, erasing and lock block operation.
Low order byte data input/output: Command user interface writing cycle data and command
Input/Output input. Various data read memory identifier and status data output Chip nonselection or
7
output disable: Float state
High order byte data input/output: The function is the same as that of low order byte
Input/Output
data input/output. Operative only in x16 mode. x8 mode: Float state DQ
14
Chip enable: Device control logic, input buffer, decoder and sense amp. are activated.
Input
Chip becomes active only when CE# is "Low".
Reset/Power down: If RP# is set to "Low", the control circuit is initialized when power
is turned on. Hence, the RP#pin is set to "Low". When power is turned on or off or in
case of fluctuation it is kept at "Low" so as to protect data from noise. When RP# is in
Input
"Low" state, the device is in deep power down state. 480 ns is required to recover
from the deep power down state. If the RP# pin becomes "Low", the whole chip operation is
interrupted and reset. After recovery the device is set to array read state.
Output enable: When OE# is set to "Low", data is output from the DQ pin. When OE# is
Input
set to "High", the DQ pin is set to float state.
Write enable: Command user interface, data Q register and address Q latch access is
Input controlled. In "Low" state WR# becomes active. At rise edge the address and data are
fetched.
Write protection: Blanking/writing to the boot block area is input of prohibition control.
Input Blanking to the boot block area and writing actuation can't be executed at the time of
WP#=V .
IL
Ready/busy: The state of internal write state machine is output. In "Low" state it is
indicated that the write state machine is in operation. If the write state machine waits for
Output
next operation instruction, erase is suspended or it is in deep power down state, the RY/BY#
pin is in float state.
Byte enable: When BYTE# is set to "Low", the device is set to the x8 mode. At this time
Input the DQ -DQ
8
When BYTE# is "High", the device is set to the x16 mode. The A
Write/erase power supply: 5.0 ± 0.5V is applied during writing/erasing.
———
Device power supply: 5.0 ± 0.5V
———
——— Ground
——— Nonconnection
Name and function
/A input circuit does not operate.)
15 -1
pin becomes float state. Address A
15
60
/A is address.
15 -1
selects high order/low order byte.
-1
input circuit is disabled.
-1