Product Information; Central Processor Unit - HP 9020 CE Handbook

9020 Product Information
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_ 9020 Product Infonnation .
Product Information
Features
• 32-bit CPU and full 32-bit internal and external data paths.
• Add-on performance with multiple CPUs.
• Up to 10 Mbytes RAM.
• 36 Mbyte/second memory processor bus.
• Four internal HP-CIO slots expandable to 20.
• Virtual memory with 500 Mbyte address space.
• Single-user or multi-user system.
• HP-UX Operating System with FORTRAN 77, Pascal, or C languages; or BASIC Language
System.
• Error correcting and self-healing memory.
• High-performance interactive graphics.
• Broad range of peripherals.
Central Processor Unit
• 32-bit single chip composed of 450,000 transistors.
• Direct address range of 500 Mbytes.
• Supports IEEE Floating Point Format.
• Instruction set of 230 operation codes.
• 18 MHz clock rate with micro-instruction cycle time of 55 ns and memory cycle time of 110 ns.
• Typical execution times:
(CPU without math chips)
Load register from memory ........................................ 550 nanoseconds
64-bit floating point multiply ...................................... 10.34 microseconds
32-bit integer multiply ............................................ 2.92 microseconds
64-bit floating point add .......................................... 5.94 microseconds
(CPU with math chips)
Floating point math chips decrease program time by performing math functions in hardware
chips. Improvement: 1.4 times faster (overall). Twice as fast on BID program.
Memory
.256 Kbyte RAM finstrates, 512K byte polystrates, or 1M byte polystrates.
• RAM memory expandable to 2.5 Mbytes.
• Single-bit error detection and correction.
• Double-bit error detection.
I/O Processor
• Supports 8
110
channels with DMA capability on every channel.
• Two additional lOPs and their associated 97098A
110
Expanders are supported.
• Nominal lOP bandwidth of 900 Kbytes/second.
• Maximum lOP bandwidth of 5.1 Mbytes/second.
09020·90035, rev.llB5