HP 9020 CE Handbook page 110

9020 Diagrams
9-7
SYSTEM CLOCK
MEMORY PROCESSOR BUS
(MPB) 1
NOTES
1 MEMORY PROCESSOR BUS INCLUDES:
ADDRESS, DATA, BUS CONTROL,POWER
AND GROUND, SELF-TEST
MISCELLANEOUS CONTROL.
2 MEMORY CONTROLLER
3 RAM BOARDS CAN BE 256K,
512K, OR PAIRS OF 1M BOARDS.
4 REQUIRED WHEN RAM IS MADE
UP OF SIX OR LESS 1 MEGABYTE
BOARDS; OR ONE CPU, ONE lOP,
AND ONE 512K RAM BOARD.
lOP BUS
CLOCK
BOARD
LOAD RESISTORS
LOAD BOARD'
CPU
FINSTRATE
CPU
THERMISTOR
Processor Stack Block Diagram