Marantz PS-17 Service Manual page 26

QK01 : AK5383
SMODE1
1
Voltage
VREFL
2
Reference
GNDL
3
VCOML
4
AINL+
Delta-Sigma
5
AINL-
Modulator
6
ZCAL
25
AINR+ Delta-Sigma
24
Modulator
AINR-
26
VCOMR
28
VREFR Voltage
27
Reference
GNDR
23 22 21
VA AGND
BGND
No. Pin Name I/O Func tion
1 VREFL O Lc h Ref erence Voltage Pin, 3.75V
Norm ally conne cted to GNDL with a 10µF el ectrolytic capacitor and a 0.1µF
ceram ic capac itor.
2 GNDL - Lc h Ref erence Ground Pin, 0V
3 VCOML O Lc h Common V oltage Pin, 2.75V
4 AINL+ I Lc h A nal og posi tive input Pin
5 AINL- I Lc h A nal og negat ive input Pin
6 ZCAL I Zero Cal ibrat ion Cont rol Pin
Thi s pi n c ont rol s the c alibrat ion ref erenc e si gnal .
" L" : VCOML and VCOMR
" H" : Anal og Input Pins (AINL+-, AINR+-)
7 VD - Digi tal Power Suppl y Pin, 3.3V
8 DGND - Digi tal Ground Pin, 0V
9 CAL O Calibrat ion A ctive Signal Pin
" H" means the offset calibrat ion cyc le is in progress . Offset calibrat ion st art s
when RS T goes " H" . CAL goe s " L" after 8704 LRCK cy cl es f or DFS=" L" ,
17408 LRCK cyc les for DFS =" H" .
10 RST I Reset Pin
When " L" , Digital sect ion is powered-down. Upon ret urni ng " H" , an of fset
calibrat ion cyc le is st art ed. An of fset calibrat ion cyc le shoul d al ways be
initiated after power-up.
11 SMODE2 I Seri al Interf ace Mode Select Pin
12 SMODE1 I MSB f irst, 2's co mp liment.
SMODE2 SMODE1 MODE LRCK
L L S lave mode : MSB justified : H/L
L H Master mode : Similar t o
H L Slave mode : I S : L/H
H H Master m ode : I S : L/H
13 LRCK I/O Left/R igh t Channel Select Cloc k Pin
LRCK goes " H" at SMODE2=" L" and " L" at SMODE2=" H" duri ng reset when
SMODE1 "H " .
14 SCLK I/O Seri al Data Clock P in
Data is cloc ked ou t on the falling edge of SCLK .
Slave mode: SCLK requi res m ore than 48f s clock.
Mast er m ode: SCLK output s a 128fs(DFS=" L" ) or 64f s(DFS=" H" ) clock.
SCLK stays " L" duri ng reset.
15 SDATA O Serial Data Outp ut Pin
MSB first , 2's complement. SDATA stays " L" duri ng res et.
16 FSYNC I/O
Fram e Synchroni zation S ignal Pin
Slave mode: When " H" , the data bits are clock ed ou t on SDATA. In I
FSYNC is Don't care.
Mast er m ode: FSYNC output s 2fs clock. FSYNC st ays " L" duri ng reset .
17 MCLK I Mast er Cl ock I nput Pin
256fs at DFS=" L" , 128fs at DFS=" H" .
18 DFS I Doubl e Speed Sampling Mode Pin
" L" : Norm al Speed
" H" : Doubl e Speed
19 HPFE I High P ass Filter Enabl e Pin
" L" : Disabl e
" H" : Enabl e
20 TEST I Test Pin ( pul l-down pi n) Shoul d be connect ed to GND.
21 BGND - Subst rate Ground Pin, 0V
22 AGND - Anal og Ground Pin, 0V
23 VA - Anal og S uppl y Pin, 5V
24 AINR- I Rch A nalog negat ive inpu t Pin
25 AINR+ I Rch A nalog posi tive inpu t Pin
26 VCOMR O Rch Common V oltage Pin, 2.75V
27 GNDR - Rch Ref erenc e Ground P in, 0V
28 VREFR O Rch Ref erenc e Voltage Pin, 3.75V
Norm ally conne cted to GNDR with a 10µF elect rol yt ic capac itor and a 0.1µF
ceram ic capac itor
FSYNC
SMODE2 SCLK LRCK
12 11 14 13 16
Serial Output
Interface
Decimation
HPF
Filter
Decimation
HPF
Filter
Calibration
Controller
SRAM
7
9 10
CAL VD
RST
2
I S : H/L
2
2
QD01 : AD1853
15
SDATA
DIGITAL
DATA INPUT
SERIAL 2
MODE
19
HPFE
17
MCLK
18
DFS
8
DGND
QU02 : ML9205-01GA
VDISP
VDD
GND
VFL
RESET
DA
CP
CS
2
S mode,
OSC0
OSC1
42
CONTROL DATA
INT2 x INT4 x INPUT
VOLUME
MUTE
3
AD1853 SERIAL CONTROL
INTERFACE
8 x Fs MULTIBIT SIGMA-
ATTEN/
DELTA MODULATOR
MUTE INTERPOLATOR
SERIAL
DATA
INTERFACE
8 x Fs MULTIBIT SIGMA-
ATTEN/
DELTA MODULATOR
MUTE
INTERPOLATOR
MUTE DE-EMPHASIS
RESET
CGROM
DCRAM
240w x 35b
24w L8b
CGRAM
16w x 35b
8-bit
ADRAM
Shift
24w x 4b
Register
Address
Selector
Command
Decoder
Write
Read
Address
Address
Counter
Counter
Control
Circuit
Digit
Control
Duty
Control
Timing
Timing
Generator1
Generator2
Oscillator
DIGITAL CLOCK
SUPPLY IN
2
VOLTAGE AUTO-CLOCK
REFERENCE DIVIDE CIRCUIT
IDAC
ANALOG
OUTPUTS
IDAC
2 2
ANALOG ZERO
SUPPLY FLAG
SEG1
Segment
Driver
SEG35
AD1
AD
Driver
AD4
P1
Port
Driver
P4
COM1
Grid
Driver
COM24