JVC KD-SX980 Service Manual page 34

KD-SX980
QQ
3 7 63 1515 0
3.Pin function (2/2)
Pin No. Symbol I/O
51 io4 I/O
52 VDD
53 io5 I/O
54 io6 I/O
55 io7 I/O
56 VSSP
57 Pdo
58 Vcoi
59 VDDP
60 Cko
61 VDDX
62 Xi
63 Xo
64 VSSX
BR24C16F-X (IC771) : EEPROM
1. Pin layout
VCC WP
TE
L 13942296513
A0 A1
3. Block diagram
A0 1
Address
A1 2
decoder
A2 3
GND 4
High voltage osc circuit
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External SRAM data input/output 4 terminal
- Digital power supply (2.5V) terminal
External SRAM data input/output 5 terminal
External SRAM data input/output 6 terminal
External SRAM data input/output 7 terminal
- VCO GND
O PLL phase error detection signal output terminal
I VCO control voltage input terminal
- VCO power supply
O 16.934 MHz clock output terminal
- Power supply (2.5V) terminal for oscillator
I Connection terminal for oscillator(input)
O Connection terminal for oscillator(output)
- GND for oscillator
2. Pin function
SCL SDA
Symbol I/O
A0,A1,A2
A2 GND
16kbit EEPROM allay
11bit
Slave Ward
11bit
Address resister
STOP
START
Control circuit
Power supply
voltage det.
x ao
y
. i
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8
Function
VCC - Power supply.
Q Q
GND - GND
3 6 7 1 3
I No use connect to GND.
SCL I Serial clock input.
SDA I/O Serial data I/O of slave and ward address.
WP I Write protect terminal.
8bit
Data
resister
ACK
u163
.
2 9 9 4 2 8
TC94A02F-005
Function
1 5 0 5 8 2 9
8 Vcc
7 WP
6 SCL
5 SDA
m
co
9 9
9 4 2 8 9 9