Sanyo VPC-E6 Service Manual page 3

3. Part of IC905 (generation of vertical transfer clock,
H Driver) and IC901 (V Driver)
An H driver (part of IC905) and V driver (IC901) are neces-
sary in order to generate the clocks (vertical transfer clock,
horizontal transfer clock and electronic shutter clock) which
driver the CCD.
IC905 has the generation of horizontal transfer clock and the
function of H driver, and is an inverter IC which drives the
horizontal CCDs (H1 and H2). It carries out generating verti-
cal transfer clock, and output to IC901.
In addition the XV1-XV6 signals which are output from IC905
are vertical transfer clocks, and the XSG signal is superim-
posed onto XV1, XV3 and XV5 at IC901 in order to generate
a ternary pulse. In addition, the XSUB signal which is output
from IC101 is used as the sweep pulse for the electronic shut-
ter, and the RG signal which is output from IC905 is the reset
gate clock.
VMSUB
9
3-level
OSUB 10
VL 5
VL 27
2-level
OV2 24
2-level
OV4 23
2-level
OV6 21
VM 8
3-level
OV1 20
28
RESET
Level
1
SUBCNT
conversion
VDC 3
Level
CH1 32
conversion
Level
V1 33
conversion
Level
V6 31
conversion
Level
V4
30
conversion
Level
V2 29
conversion
Level
V5R 37
conversion
Level
V5L 38
conversion
Level
35
V3R
conversion
Level
V3L 36
conversion
Level
V1S 34
conversion
Fig. 1-3. IC901 Block Diagram
4. IC905 (H Driver, CDS, AGC and A/D converter)
IC905 contains the functions of H driver, CDS, AGC and A/D
converter. As horizontal clock driver for CCD image sensor,
HØ1 (A and B) and HØ2 (A and B) are generated inside, and
output to CCD.
The video signal which is output from the CCD is input to pin
(A6) of IC905. There are sampling hold blocks generated from
the SHP and SHD pulses, and it is here that CDS (correlated
double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier (VGA: Variable Gain Amplifier). It
is A/D converted internally into a 14-bit signal, and is then
input to ASIC (IC101). The gain of the VGA amplifier is con-
trolled by pin (A2), (B3) and (C4) serial signal which is output
from ASIC (IC101).
7
VHH
2-level
16 OV5R
2-level
15
OV5L
1.8V OUTPUT
2-level
1.8V INPUT
18
OV3R
3V OUTPUT
2-level
17
OV3L
2-level
19
OV1S
XV1 TO XV24
25 VM
3-level
12
OV5A
3-level
11 OV5B
3-level
14 OV3A
3-level
13 OV3B
6 VH
26 VH
4 GND
Level
41
CH2
conversion
Level
40
V3
conversion
Level
39
CH4
conversion
Level
44 CH3
conversion
Level
43
V5
conversion
Level
42 CH5
conversion
Level
2 SUB
conversion
– 3 –
6~42 dB
VGA
CDS
CCDIN
-3dB, 0dB, +3dB
3V INPUT
LDO
REG
INTERNAL
CLOCKS
CHARGE
PUMP
RG
PRECISION
HORIZONTAL
HL
TIMING
DRIVERS
8
GENERATOR
H1 TO H8
24
VERTICAL
SYNC
TIMING
GENERATOR
XSUBCK
CONTROL
8
HD VD
GP01 TO GP08
Fig. 1-4. IC905 Block Diagram
REFT REFB
AD9996
VREF
14
14-BIT
DOUT
ADC
CLAMP
SL
INTERNAL
SCK
REGISTERS
SDI
CLI CLO
SYNC