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DIGITAL 5 0
PHY_RESET[L]
5
PHY_LREQ PHY_CLK
PHY_CNA PHY_CTL[0],[1]
PHY_DATA[0-7] PHY_LPS
PHY_LINK_ON
SDRAM_A_17
4
SDRAM_DQ0 to 15
SDRAM_A0 to 15
SDRAM_CKE
SDRAM_RAS_L
SDRAM_CAS_L
SDRAM_WE_L
SDRAM_DQM0 to 3
3
SDRAM_DQS0 to 3
SDRAM_CLK0,1
SDRAM_CLK_L0,1
2
1
A
2-7
IEEE1394
controller
IC1801
IEEE1394 section (SHEET 8)
SDRAM_DQ16 to 31
RA1613 to
RA1609 to
RA1612
RA1625 to
RA1635
R1601 to R1604
E5_RESET_L VI_D2 to D9 VIDEO_27M SIO_SCL SIO_SDA
AI_SCLK AI_FSYNC AI_MCLKO V_Y_OUT SY_OUT SC_OUT
Media
G_Y_OUT B_PB_OUT R_PR_OUT AO_D_0 AO_SCLK AO_FSYNC
processor
AO_IEC958 AO_MCLK AI_D_0 SPI_CLK A_DAC_CS SPI_MOSI
IC1401
A_MUTE2_H G_TX G_RX IRTX K_BUS_CLK K_BUS_REQ
SYS_RESET_L K_BUS_OUT K_BUS_IN DAC_RST_L
ATA_DMAACK[L] ATA_INTRQ ATA_ADD0 to 4
ATA_DIOR[L] ATA_DIOW[L] ATA_IORDY
ATA_DAT0 to 15 ATA_RESET ATA_DMARQ
RD/WR[L] ALE OE[L]/LDS[L] MADD1 to 22 CS[0] E5_RESET[L]
Media processor (SHEET 10)
B
TPA+ TPA- TPB+ TPB-
DDR_DQ16 to 31
RA1616
DDR SDRAM
DDR_DQ0 to 15
IC1601
RA1628
RA1634
DDR_DQM0 to 3
DDR_DQS0 to 3
DDR_CLK0,1
DDR_CLK_L0,1
R1606 to
R1609
DDR SDRAM section (SHEET 9)
DDR SDRAM
IC1602
DDR_BA0,1
DDR_A0 to 12
DDR_CKE
DDR_RAS_L
DDR_CAS_L
DDR_WE_L
C
J4112
IEEE1394
terminal
D
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