JVC DR-MH20SE Service Manual page 27

Media processor section
AO_D[0]
AO_SCLK
AO_FSYNC
TO SHEET 5
AO_IEC958
AO_MCLKO
AI_D[0]
VIDEO_MUTE[H]
TO SHEET 2
PHY_CNA
480I[H]
TO SHEET 5
5
## B1404
## B1405
R1408 1k
D3.3V R1409 10k
R1410 10k
TL1407
R1411 100
R1412 10k
R1413 10k
VI_D[2]
VI_D[3]
VI_D[4]
VI_D[5]
VI_D[6]
VI_D[7]
VI_D[8]
VI_D[9]
R1414
R1415
V3.3V
R1416
K1407 R1417
4 SHORT
R1402
0Ω
R1494
R1495
C1450
0.1
X1401
NAX0580-001X
VO_D[0]
VO_D[1]
VO_D[2]
VO_D[3]
VO_D[4]
VO_D[5]
VO_D[6]
VO_D[7]
VO_D[8]
VO_D[9]
VO_D[10]
VO_D[11]
VO_D[12]
VO_D[13]
VO_D[14]
VO_D[15]
R1419
TL1412
VI_D[2-9]
VI_D[2-9] TL1490
VO_D[0-15]
TL1491
VO_D[0-15]
R1420
VIDEO_27M
# R1421 OPEN # R1485 OPEN
TO DAC_CVBS_OUT
3
# R1422 OPEN # R1486 OPEN
DAC_SY_OUT
# R1423 OPEN # R1487 OPEN
DAC_SC_OUT
SHEET 5
# R1424 OPEN # R1488 OPEN
DAC_Y_OUT
# R1425 OPEN # R1489 OPEN
DAC_PB_OUT
# R1426 OPEN # R1490 OPEN
DAC_PR_OUT
C1452 0.1
V3.3V
R1493
0Ω
0.1
K1408 C1453
SHORT
# C1454 D1401 D1402
OPEN
C1455 0.1
# C1456
OPEN
TL1413
TL1414
TL1415
R1491 1k
TL1417
TL1418
TL1419
R1427 100 TL1420
PHY_DATA[7]
PHY_DATA[6]
PHY_DATA[5]
PHY_DATA[4]
PHY_DATA[3]
PHY_DATA[2]
PHY_DATA[1]
PHY_DATA[0-7] PHY_DATA[0]
PHY_DATA[0-7]
TO
R1428 100
PHY_CTL[1]
2 R1429 100
PHY_CTL[0]
SHEET 2 R1430 100
PHY_LREQ
R1431 100
PHY_LPS
PHY_LINK_ON
PHY_CLK
# R1432 OPEN
TO
DIGI3.3V
D2.5V
# B1401
SHEET 5 D1.8V
LC1401
GND OPEN NQR0512-008x
C1401 C1402 C1404 C1405 C1406 C1417
0.1 0.1 47 0.1 0.1 0.1
/6.3
# B1402 LC1402
OPEN NQR0512-008X
D5.0V C1408 C1409 C1411 C1412
TO D5.0V 0.1 0.1 100 0.1
/6.3
D1.8V
# B1403 LC1403
D2.5V OPEN NQR0512-008X C1415 C1461
SHEET 5 OPEN 0.1
DIGI3.3V
GND
C1416
GND
0.1
C1413 C1414
47 0.1
/6.3
TO SHEET 3
D3.3V C1464 C1465 C1466 C1467 C1468 C1469 C1470 C1471 C1472 C1473 C1474
0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1
VDDI1.8
TO SHEET 5
GND
1
A
CLKI
TL1402
CLKX
TL1437
CLKO_DAC/GPIOExt[35]
BYPASS_PLL
TL1403
EPD[L]
TL1404
RSTO[L]
TCK
TDI
TDO
TMS
TRST[L]
VI_D[0]
VI_D[1]
VI_D[2]
VI_D[3]
VI_D[4]
VI_D[5]
VI_D[6]
VI_D[7]
VI_D[8]
VI_D[9]
1k
VI_E[0]
1k
VI_VSYNC[0]
VI_CLK[0]
1k
VI_CLK[1]
1k
VI_VSYNC[1]/IvGPIOExt[45]
TL1489
VI_E[1]/IvGPIOExt[29]
10k
VO2_D[0]
10k
VO2_D[1]
TL1452
VO2_D[2]
TL1453
VO2_D[3]
TL1454
VO2_D[4]
TL1455
VO2_D[5]
TL1456
VO2_D[6]
TL1457
VO2_D[7]
TL1458
VO2_D[8]
TL1459
VO2_D[9]
VO_D[0]/IvGPIOExt[0]
VO_D[1]/IvGPIOExt[1]
RA1401
VO_D[2]/IvGPIOExt[2]
100
VO_D[3]/IvGPIOExt[3]
VO_D[4]/IvGPIOExt[4]
VO_D[5]/IvGPIOExt[5]
RA1402
VO_D[6]/IvGPIOExt[6]
100
VO_D[7]/IvGPIOExt[7]
VO_D[8]/IvGPIOExt[8]
VO_D[9]/IvGPIOExt[9]
RA1403
VO_D[10]/IvGPIOExt[10]
100
VO_D[11]/IvGPIOExt[11]
VO_D[12]/IvGPIOExt[12]
VO_D[13]/IvGPIOExt[13]
RA1404
VO_D[14]/IvGPIOExt[14]
100
VO_D[15]/IvGPIOExt[15]
100
VO_E/IvGPIOExt[30]
VO_ACTIVE
VO_HSYNC
VO_VSYNC
100
VO_CLK
DAC1_OUT
DAC2_OUT
DAC3_OUT
DAC4_OUT
DAC5_OUT
DAC6_OUT
DAC_DVSS_1
DAC_DVDD
DAC_VDD_0
DAC_VDD_3
DAC4_OUTB
DAC2_OUTB
USB_AVDD_0
USB_AVDD_1
USB_AGND_0
USB_AGND_1
DPLUS_0
DMINUS_0
HOST_PO_0
HOST_OC_0
DPLUS_1
DMINUS_1
HOST_PO_1/GPIOExt[43]
HOST_OC_1/GPIOExt[44]
USB_48MHz/GPIOExt[36]
1394_PHY_DATA[7]
1394_PHY_DATA[6]
RA1405
1394_PHY_DATA[5]
100
1394_PHY_DATA[4]
1394_PHY_DATA[3]
1394_PHY_DATA[2]
RA1406
1394_PHY_DATA[1]
100
1394_PHY_DATA[0]
1394_PHY_CTL[1]
1394_PHY_CTL[0]
1394_LREQ
1394_LPS
1394_LINK_ON
1394_PHY_CLK
K1402
SHORT
T T
C1442
0.1
C1418 C1419 C1420 C1421 C1422 C1423 C1424 C1425 K1403
0.1 OPEN 10 0.1 0.1 0.1 0.1 0.1 SHORT
/6.3
SSTL2_VDD
C1444
# K1404 0.1
T
C1427 C1428 C1429 C1430
10 0.1 0.1 0.1
/6.3
K1401
K1406
C1463 SHORT # K1405 SHORT
0.1
T T
C1434 C1435 C1436 C1437 C1438 C1439 C1445 C1446
OPEN 10 0.1 0.1 0.1 0.1 0.1 0.1
/6.3
C1475
0.1
TO SHEET 6
TO SHEET 3
B C
IC1401
DMN8652-B0
Not use
TO SHEET 5
D E
2-17 2-18
R1471 100
ALE
R1470 1k R1472 0Ω
RST[L]
R1469 1k C1459 OPEN
MCONFIG
CS0_8BIT
R1468 100
LDS[L]/OE[L]
R1467 100
UDS[L]/UWE[L]
R1466 100
GPIO[0]
R1465 100
GPIO[1]
TL1486
GPIO[2]
TL1485
GPIO[3]
R1462 100
GPIO[4] /PCMCIA_IOW[L]
R1461 100
GPIO[5] /PCMCIA_IOR[L]
R1460 100
WR[L]/LWE[L]
R1459 100
WAIT[L]
R1458 100
DTACK[L]
TL1484
CS[5]
TL1483
CS[4]
TL1482
CS[3]
TL1481
CS[2]
R1453 100 CS[1]
CS[1]
R1452 100 CS[0]
CS[0]
TL1480
MADDR[26]
TL1479
MADDR[25]
TL1478
MADDR[24]
TL1477
MADDR[23]
R1451 100 MADD[22]
MADDR[22]
R1450 100 MADD[5]
MADDR[5]
MADD[4]
MADDR[4]
RA1411 MADD[3]
MADDR[3]
100 MADD[2]
MADDR[2]
MADD[1]
MADDR[1]
MADD[21]
MADDR[21]/MDATA[15]
RA1410 MADD[20]
MADDR[20]/MDATA[14]
100 MADD[19]
MADDR[19]/MDATA[13]
MADD[18]
MADDR[18]/MDATA[12]
MADD[17]
MADDR[17]/MDATA[11]
RA1409 MADD[16]
MADDR[16]/MDATA[10]
100 MADD[15]
MADDR[15]/MDATA[9]
MADD[14]
MADDR[14]/MDATA[8]
MADD[13]
MADDR[13]/MDATA[7]
RA1408 MADD[12]
MADDR[12]/MDATA[6]
100 MADD[11]
MADDR[11]/MDATA[5]
MADD[10]
MADDR[10]/MDATA[4]
MADD[9]
MADDR[9]/MDATA[3]
RA1407 MADD[8]
MADDR[8]/MDATA[2]
100 MADD[7]
MADDR[7]/MDATA[1]
MADD[6]
MADDR[6]/MDATA[0]
ATA_ADD[0]
ATAPI_ADDR[0]
ATA_ADD[1]
ATAPI_ADDR[1]
ATA_ADD[2]
ATAPI_ADDR[2]
ATA_ADD[3]
ATAPI_ADDR[3]
ATA_ADD[4]
ATAPI_ADDR[4]
ATA_DAT[15]
ATAPI_DATA[15]
ATA_DAT[14]
ATAPI_DATA[14]
ATA_DAT[13]
ATAPI_DATA[13]
ATA_DAT[12]
ATAPI_DATA[12]
ATA_DAT[11]
ATAPI_DATA[11]
ATA_DAT[10]
ATAPI_DATA[10]
ATA_DAT[9]
ATAPI_DATA[9]
ATA_DAT[8]
ATAPI_DATA[8]
ATA_DAT[7]
ATAPI_DATA[7]
ATA_DAT[6]
ATAPI_DATA[6]
ATA_DAT[5]
ATAPI_DATA[5]
ATA_DAT[4]
ATAPI_DATA[4]
ATA_DAT[3]
ATAPI_DATA[3]
ATA_DAT[2]
ATAPI_DATA[2]
ATA_DAT[1]
ATAPI_DATA[1]
ATA_DAT[0]
ATAPI_DATA[0]
ATAPI_RESET
ATAPI_DMAACK[L]
ATAPI_DMARQ
ATAPI_IORDY
ATAPI_INTRQ
ATAPI_DIOR[L]
ATAPI_DIOW[L]
ATAPI2_RESET
ATAPI2_DMAACK[L]
ATAPI2_DMARQ
ATAPI2_IORDY
ATAPI2_INTRQ
ATAPI2_DIOR[L]
ATAPI2_DIOW[L]
ATA2_ADD[0]
ATAPI2_ADDR[0]
ATA2_ADD[1]
ATAPI2_ADDR[1]
ATA2_ADD[2]
ATAPI2_ADDR[2]
ATA2_ADD[3]
ATAPI2_ADDR[3]
ATA2_ADD[4]
ATAPI2_ADDR[4]
ATA2_DAT[15]
ATAPI2_DATA[15]
ATA2_DAT[14]
ATAPI2_DATA[14]
ATA2_DAT[13]
ATAPI2_DATA[13]
ATA2_DAT[12]
ATAPI2_DATA[12]
ATA2_DAT[11]
ATAPI2_DATA[11]
ATA2_DAT[10]
ATAPI2_DATA[10]
ATA2_DAT[9]
ATAPI2_DATA[9]
ATA2_DAT[8]
ATAPI2_DATA[8]
ATA2_DAT[7]
ATAPI2_DATA[7]
ATA2_DAT[6]
ATAPI2_DATA[6]
ATA2_DAT[5]
ATAPI2_DATA[5]
ATA2_DAT[4]
ATAPI2_DATA[4]
ATA2_DAT[3]
ATAPI2_DATA[3]
ATA2_DAT[2]
ATAPI2_DATA[2]
ATA2_DAT[1]
ATAPI2_DATA[1]
ATA2_DAT[0]
ATAPI2_DATA[0]
D1403
R1441
10k
C1457 C1458
0.1 0.1
TO SHEET 5
F
SDRAM_A[14-17]
SDRAM_VREF
SDRAM_CLK_L[1] SDRAM_A[14-17]
SDRAM_CLK_L[1]
SDRAM_CLK[1]
SDRAM_CLK[1]
SDRAM_CLK_L[0]
SDRAM_CLK_L[0]
SDRAM_CLK[0]
SDRAM_CLK[0] TO
SDRAM_WE_L
SDRAM_WE_L
SDRAM_CKE
SDRAM_CKE
SHEET 3
SDRAM_RAS_L
SDRAM_RAS_L
SDRAM_CAS_L
SDRAM_CAS_L
SDRAM_DQM[0-3]
SDRAM_DQM[0-3]
SDRAM_DQS[0-3]
SDRAM_DQS[0-3]
SDRAM_A[0-13]
SDRAM_A[0-13]
SDRAM_DQ[16-31]
SDRAM_DQ[16-31]
SDRAM_DQ[0-15]
SDRAM_DQ[0-15]
ALE
OE[L]/LDS[L]
UWE[L]/UDS[L]
ELINK_INT[L]
RD/WR[L] TO
WAIT[L]
DTACK[L]
SHEET 7
CS[1]
CS[0]
MADD[22]
MADD[1-5]
MADD[1-5]
MADD[6-21]
MADD[6-21]
/MDT[0-15]
PHY_RESET[L]
TO
SHEET 2
ATA_ADD[0-4]
ATA_ADD[0-4]
ATA_DAT[0-15]
ATA_DAT[0-15]
ATA_RESET
ATA_DMAACK[L]
ATA_DMARQ
ATA_IORDY
ATA_INTRQ
ATA_DIOR[L]
TO
ATA_DIOW[L]
ATA2_RESET
SHEET 6
ATA2_DMAACK[L]
ATA2_DMARQ
ATA2_IORDY
ATA2_INTRQ
ATA2_DIOR[L]
ATA2_DIOW[L]
ATA2_ADD[0-4]
ATA2_DAT[0-15]
ATA2_DAT[0-15]
DAC_RST[L]
R1445 100
K_BUS_CLK
TO
R1446 100
K_BUS_REQ
R1447 100
SYS_RESET[L]
R1448 100 SHEET 5
K_BUS_OUT
R1449 100
K_BUS_IN
TO
E5_RESET[L]
UART2_TX
UART2_RX SHEET 7
p10613001a_rev0
SHEET 4
G