Download  Print this page

Block Diagrams - JVC DR-MH20SE Service Manual

Dvd&hdd video recorder.
Hide thumbs

Advertisement

Block diagrams

DIGITAL 0 2
IEEE1394
Controller
PHY_RESET[L]
5
IC1801
PHY_LREQ PHY_CLK
PHY_CNA PHY_CTL[0],[1]
PHY_DATA[0-7] PHY_LPS
PHY_LINK_ON
IEEE1394 Section (SHEET 2)
RA1613 to
SDRAM_DQ16 to 31
RA1616
SDRAM_DQ0 to 15
4
RA1609 to
RA1612
DDR_CS0
RA1642
DDR_CS1
RA1641
SDRAM_A0 to 15
RA1625 to
RA1628
SDRAM_DQM0 to 3
DDR_DQM0 to 3
SDRAM_DQS0 to 3
RA1601 to
DDR_DQS0 to 3
3
RA1604
SDRAM_CKE
SDRAM_RAS_L
DDR_RAS_L DDR_CKE
SDRAM_CAS_L
DDR_CAS_L DDR_WE_L
SDRAM_WE_L
RA1653 to
RA1660
SDRAM_CLK0,1
DDR_CLK0,1
SDRAM_CLK_L0,1
DDR_CLK_L0,1
RA1613 to
RA1616
2
Media
processor
IC1401
IC1404
IC1405
1
Media processor section (SHEET 4)
A
TPA+ TPA- TPB+ TPB-
DDR_DQ16 to 31
DDR_DQ0 to 15
DDR SDRAM
DDR SDRAM
DDR SDRAM
IC1601
IC1602
IC1603
DDR_BA1,2
DDR_A0 to 12
DDR SDRAM Section (SHEET 3)
ATA2_DMAACK[L] ATA2_INTRQ ATA2_ADD0 to 4
ATA2_DIOR[L] ATA2_DIOW[L] ATA2_IORDY
ATA2_DAT0 to 15 ATA2_RESET ATA2_DMARQ
ATA_DMAACK[L] ATA_INTRQ ATA_ADD0 to 4
ATA_DIOR[L] ATA_DIOW[L] ATA_IORDY
ATA_DAT0 to 15 ATA_RESET ATA_DMARQ
SYS_RESET[L] VIDEO_RXD
K_BUS_CLK K_BUS_REQ K_BUS_IN/OUT
VIDEO_RST[L] SPI_MOSI SPI_CLK VIDEO_CS
RD/WR[L] ALE OE[L]/LDS[L] MADD1 to 22 CS[0] E5_RESET[L]
B
C
J4112
IEEE1394
Terminal
TO CN4101
SHEET 10
DDR SDRAM
TO CN4102
IC1604
SHEET 10
ATA2_DATA0 to 15
ATA2_RESET ATA2_DMARQ
ATA2_IORDY ATA2_INTRQ
ATA2_DMAACK[L] ATA2_ADD0 to 4
ATA2_DIOW[L] ATA2_DIOR[L]
ATA_DATA0 to 15
ATA_RESET ATA_DMARQ
ATA_IORDY ATA_INTRQ
ATA_DMAACK[L] ATA_ADD0 to 4
ATA_DIOW[L] ATA_DIOR[L]
P_CTL[H]
D
E
2-5
2-6
CIN VYIN SYNCDET CROUT CBOUT
YVOUT COUT
AO_FSYNC AO_D[0] DAC_RST[L]
AO_SCLK A_DAC_CS AO_MCLKO
DAC_CVBS_OUT
DAC_SCL DAC_Y_OUT
DAC_SY_OUT
DAC_RST[L] 480I[H]
DAC_SC_OUT
VI_D2 to 9 VIDEO_RST[L] VO_D1 to 15
SPI_MOSI
VIDEO_27M VIDEO_CS VIDEO_MUTE[M] SPI_CLK VIDEO_RXD
SYS_RESET[L] K_BUS_CLK K_BUS_REQ K_BUS_IN K_BUS_OUT
AO_IEC958 AI_D[0] A_MUTE2[H] DAC_CSL DAC_SDA
Video signal control section (SHEET 5)
RSTATA DMARQ IORDY
HD_AT0 to 15 INT_ATA
ATA_A0 to 2 CS1FX CS3FX
DIOW DIOR DMACK
RSTATA DMARQ IORDY
HD_AT0 to 15 INT_ATA
20bit FET
Bus switch
IC2201
ATA_A0 to 2 CS1FX CS3FX
DIOW DIOR DMACK
8bit FET
Bus switch
Q2201
IC2202
ATAPI Interface section (SHEET 6)
MADD1 to 22
16Mbit Flash
RD/WR[L] E5_RESET[L] OE[L]/LDS[L] CS[0]
ALE MADD6 to 21
FLASH-ROM Section (SHEET 7)
F
Video
controller
IC1001
AP A0 to A9
UDQM WE
CAS RAS
DQ0 to DQ15
16M SDRAM
IC1002
TO
HDD unit
TO
DVD-RAM
DRIVE
IC1201
LH_AR6 to 21
IC1202
IC1203
G

Advertisement

Table of Contents

   Also See for JVC DR-MH20SE

   Related Manuals for JVC DR-MH20SE

Comments to this Manuals

Symbols: 0
Latest comments: