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4.1.9.3 ECC Configuration Submenu
Feature
Master
ECC Enable
DRAM
ECC Enable
L2 Cache
BG Scrub
Date Cache
BG Scrub
Options
Description
Disabled
Master ECC Enables support on all nodes for ECC
Enabled
error detect and correction.
DRAM ECC allows hardware to report and correct
Disabled
memory errors automatically maintaining system
Enabled
integrity.
Disable
40ns
80ns
160ns
320ns
640ns
1.28us
2.56us
Allows the L2 date cache ram to be corrected
5.12us
while idle.
10.2us
20.5us
41.0us
81.9us
163.8us
327.7us
655.4us
See above
Allows the L1 date cache ram to be corrected
while idle.
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