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IC BLOCK DIAGRAM & DESCRIPTION
IC102 ADV7170KSU(VIDEO ENCODER)
44 43 42 41 40
39 38 37
36 35 34
V
1
AA
PIN 1
P5
2
IDENTIFIER
P6
3
P7
4
P8
5
ADV7170/ADV7171
PQFP/TQFP
P9
6
TOP VIEW
P10
7
(Not to Scale)
P11
8
P12
9
GND
10
11
V
AA
12 13 14 15 16
17 18 19
20 21 22
Input/
Mnemonic
Output
P15-P0
I
CLOCK
I
HSYNC
I/O
FIELD/VSYNC
I/O
BLACK
I/O
SCRESET/RTC
I
V
I/O
REF
R
I
SET
COMP
O
DAC A
O
DAC C
O
DAC D
O
DAC B
O
SCLOCK
I
SDATA
I/O
ALSB
I
RESET
I
TTX/V
I
AA
TTXREQ/GND
O
V
P
AA
GND
G
POWER
MANAGEMENT
33
V
REF
CONTROL
Vss
1,11,20,28,30
(SLEEP MODE)
32
DAC A
31
DAC B
RESET
22
30
V
AA
CLOCK
29
GND
DATA
4-2
V
28
AA
P7-P0
4:2:2 TO
43-38
4:4:4
27
DAC D
INTER-
14-12
P15-P8
POLATOR
9-5
26
DAC C
25
COMP
24
SDATA
HSYNC
15
VIDEO TIMING
23
SCLOCK
FIELD/VSYNC
16
GENERATOR
BLANK
17
44
CLOCK
PIN FUNCTION DESCRIPTIONS
Function
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7-P0) or 16-Bit YCrCb Pixel Port (P15-P0).
P0 represents the LSB.
TTL Clock Input. Requires a stable 27 MHz reference Clock for standard operation. Alter-
natively, a 24.52 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.
HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to output (Master
Mode) or accept (Slave Mode) Sync signals.
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be
configured to output (Master Mode) or accept (Slave Mode) these control signals.
Video Blanking Control Signal. The pixel inputs are ignored when this is Logic Level "0."
This signal is optional.
This pin can be configured as an input by setting MR22 and MR21 of Mode Register 2. It
can be configured as a subcarrier reset pin, in which case a high-to-low transition on this
pin will reset the subcarrier to Field 0. Alternatively, it may be configured as a Real-Time
Control (RTC) input.
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
A 150
resistor connected from this pin to GND is used to control full-scale amplitudes of
the video signals.
Compensation Pin. Connect a 0.1 F Capacitor from COMP to VAA. For Optimum Dynamic
Performance in low power mode, the value of the COMP capacitor can be lowered to as low
as 2.2 nF.
PAL/NTSC Composite Video Output. Full-Scale Output is 180 IRE (1286 mV) for NTSC
and 1300 mV for PAL.
RED/S-Video C/V Analog Output.
GREEN/S-Video Y/Y Analog Output.
BLUE/Composite/U Analog Output.
MPU Port Serial Interface Clock Input.
MPU Port Serial Data Input/Output.
TTL Address Input. This signal set up the LSB of the MPU address.
The input resets the on chip timing generator and sets the ADV7170/ADV7171 into default
mode. This is NTSC operation, Timing Slave Mode 0, 8 Bit Operation, 2 x Composite and
S Video out and DAC B powered ON and DAC D powered OFF.
Teletext Data/Defaults to VAA When Teletext not Selected (enables backward compatibility to
ADV7175/ADV7176).
Teletext Data Request Signal/ Defaults to GND when Teletext not Selected (enables backward
compatibility to ADV7175/ADV7176).
Power Supply (+3V to +5V).
Ground Pin.
TTXREQ
TTX
36
37
CGMS & WSS
TELETEXT
INSERTION
INSERTION
BLOCK
BLOCK
Y
9
9
8
8
ADD
INTER-
SYNC
POLATOR
YCrCb
TO
8
8
8
8
U
YUV
MATRIX
ADD
INTER-
8
8
8
V
8
BURST
POLATOR
2
I C MPU PORT
23
24
18
SCLOCK
SDATA
ALSB
SCRESET/RTC
- 56 -
M
10
U
L
T
YUV TO
10
I
RBG
P
MATRIX
L
10
E
X
E
PROGRAMMABLE
10
R
LUMINANCE
FILTER
10
U
PROGRAMMABLE
CHROMINANCE
10
V
FILTER
10
10
REAL-TIME
SIN/COS
CONTROL
DDS BLOCK
REFERENCE
CIRCUIT
35
10,19,29,43
GND
10
10-BIT
DAC D(PIN 27)
27
DAC
10
10-BIT
26
DAC C(PIN 26)
DAC
10
10-BIT
GAC B(PIN 31)
31
DAC
10
10-BIT
DAC A(PIN 32)
32
DAC
33
V
REF
VOLTAGE
R
34
SET
CIRCUIT
25
COMP
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