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IC BLOCK DIAGRAM & DESCRIPTION
IC118 LE28DW8102T-90-MPB(FLASH MEMORY)
1
A15
2
A14
3
A13
4
A12
5
A11
6
A10
7
A9
8
A8
9
WE#
10
NC
11
NC
12
NC
13
NC
14
NC
15
NC
16
A18
17
A17
18
A78
19
A6
20
A5
21
A4
22
A3
23
A2
24
ACE#
STM.
A18
Bank Selective Address
A17-A0
Flush Bank Address
A17-A15
Flush Bank Block Address
A17-A10
Flush Bank Sector Sddress
DQ15-DQ0
Data Input/Output
CE#
Chip Enable
OE#
Output Enable
WE#
Write Enable
VDD
Power Supply
GND
Ground
NC
No Connection
IC475 LA4663)POWER IC)
STAND BY
5
SIGNAL
6
MUTE
IN1
2
PRE
3
GND
IN2
4
1
Rlpple Filter/
Starting Time
48
A16
47
VSS
CHARGE PUMP
46
DQ15
&
45
DQ7
VOLTAGE
44
DQ14
REFERENCE
43
DQ6
CIRCUIT
42
DQ13
41
DQ5
40
DQ12
ADDRESS BUFFER
39
DQ4
&
38
NC
LATCH CIRCUIT
37
VDD
36
DQ11
35
DQ3
34
DQ10
A18-A0
33
DQ2
32
DQ9
31
DQ1
CE#
30
DQ8
CONTROL LOGIC
OE#
29
DQ0
28
OE#
WE#
27
VSS
26
A0
25
A1
NAME
Selects bank 1 when "L" and bank 2 when "H".
Sapply address for flush bank.
Select flush bank for erease.
Select flush bank sector for erease.
To output data during read cycle and receive input data during write
cycles. Data is internaliy latched during a writecycle. The output are
high inpedance when OE#,CE# is high.
To activate the flush bank when CE# is low.
To activate the data output buffer .
To control the write, erease and program.
207V~3.6V supply.
Not connect to internal chip.
Vcc1 Vcc2
7
8
14
+OUT1
PWR
13
GND1
12
-OUT1
9
+OUT2
PWR
10
GND2
11
-OUT2
COLUMN DECODER
LOW DECODER
DQ15.DQ0
FUNCTION
- 61 -
256Kx16
FLUSH
BANK1
256Kx16
FLUSH
BANK2
IN/OUTPUT BUFFER
&
DATA LATCH
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