LG 55X6500-TD Service Manual page 45

Led lcd tv
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MAIN 3.3V & 3.3V IO POWER
VLCD_POWER
L301
IC301
120-ohm
MP8706EN-C247-LF-Z
IN
GND
1
8
C308
1uF
C311
SW_1
VCC
2
7
50V
100pF
C301
50V
22uF
SW_2
FB
25V
3
6
C302
VLCD_POWER
0.1uF
BST
EN/SYNC
4
5
R307
R301
100K
22
C309
R306
0.47uF
39K
50V
OPT
L305
3.6uH
4.9A
1.0V DIGITAL CORE POWER
+3.3V
L303
120-ohm
R305
100K
IC302
MP2212DN
C304
R302
100pF
3K
1%
R1
FB
EN/SYNC
1
8
R303
Vout= 0.8*(1+R1/R2)
9.1K
1%
GND
SW_2
2
7
R2
IN
SW_1
3
6
BS
VCC
C303
C306
4
5
22uF
10uF
16V
6.3V
OPT
R304
10
1%
VLCD_POWER
(+12V)
IC303
BCD_REGULATOR
AOZ1072AI
L315
PGND
LX_2
CIC21J501NE
1
8
BCD_REGULATOR
VIN
LX_1
2
7
C380
2A
BCD_REGULATOR
0.1uF
AGND
EN
BCD_REGULATOR
3
6
C378
C379
BCD_REGULATOR
10uF
10uF
FB
DEV
COMP
25V
25V
4
5
BCD_REGULATOR
12K
BCD_REGULATOR
R339
EAN60922901
BCD_REGULATOR
Vout=0.8*(1+R1/R2)
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
DDR2 SDRAM SOURCE POWER for FRC
VLCD_POWER
(+12V)
+3.3V
L304
120-ohm
Vout= 0.8*(1+R1/R2)
R308
39K
C377
C374
C317
1%
22uF
22uF
22uF
R1
OPT
16V
16V
16V
R309
(+12V)
12.4K
1%
R2
C314
0.01uF
50V
+1.0VDC
L306
3.6uH
NR8040T3R6N
C316
C318
C319
C315
22uF
22uF
0.1uF
0.1uF
16V
16V
16V
50V
C312
1uF
10V
1.2V FPGA CORE POWER
MAX 350mA
+5V_NORMAL
L316
3.6uH
BCD_REGULATOR
NR8040T3R6N
VLCD_POWER
(+12V)
BCD_REGULATOR
BCD_REGULATOR
BCD_REGULATOR
C382
C383
C385
R1
22uF
22uF
0.1uF
10V
10V
16V
BCD_REGULATOR
BCD_REGULATOR
OPT
C381
C384
2200pF
100pF
50V
BCD_REGULATOR
R2
BCD_REGULATOR
C330
C334
1uF
25V
0.1uF
50V
C320
10uF
25V
LX_1
PGOOD
22
15
LX_2
20
R310
LX_3
100K
EN/PSV
25
21
LX_4
R320
C338
P3
8.2K
0.1uF
IC304
50V
ENL
28
SC424MLTRT
LXBST
12
LXS
FB
1
24
ILIM
23
C325
TON
0.1uF
27
16V
BST
7
R318
100K
DDR2 SDRAM SOURCE POWER for FPGA
VLCD_POWER
L310
IC310
120-ohm
MP8706EN-C247-LF-Z
Vout= 0.8*(1+R1/R2)
IN
GND
1
8
C335
C339
1uF
SW_1
VCC
2
7
50V
100pF
C321
50V
OPT
22uF
SW_2
FB
25V
3
6
C326
VLCD_POWER
0.1uF
BST
EN/SYNC
4
5
(+12V)
R321
R311
100K
22
C337
R319
0.47uF
39K
50V
L314
3.6uH
4.9A
+3.3V
Vout= 0.8*(1+R1/R2)
L308
120-ohm
R314
100K
C327
100pF
R312
R313
R317
10K
0
5.1K
IC305
MP2212DN
FB
EN/SYNC
1
8
L309
3.6uH
GND
SW_2
2
7
IN
SW_1
3
6
OPT
C322
C323
C324
22uF
0.1uF
22uF
BS
VCC
4
5
16V
50V
16V
OPT
D302
R315
1N4148W_DIODES
10
100V
C328
R316
0.1uF
10
C329
1uF
25V
+2.5VQ
+5V_NORMAL
L317
120-ohm
BCD_REGULATOR
R347
1K
BCD_REGULATOR
C386
10uF
C387
0.1uF
16V
VLCD_POWER
(+12V)
+2.5VQ
L307
3.3uH
4.1A
OPT
C371
C372
C373
R334
C368
0.01uF
22uF
22uF
22uF
39K
16V
16V
16V
OPT
OPT
OPT
+2.5VQ
+5V_NORMAL
C340
C369
R335
1000pF
10K
100pF
OPT
1%
50V
L318
R1
120-ohm
BCD_REGULATOR
R355
1K
BCD_REGULATOR
C392
10uF
C393
0.1uF
16V
R338
4.3K
1%
R2
VLCD_POWER
(+12V)
OPT
OPT
2V5
VOUT=0.6*(R1+R2)/R2
C375
C376
C370
R336
10K
22uF
22uF
22uF
1%
16V
16V
16V
R1
2V5
+5V_NORMAL
R337
4.7K
1%
L319
R2
120-ohm
BCD_REGULATOR
R364
0
BCD_REGULATOR
C398
10uF
C399
0.1uF
16V
VLCD_POWER
(+12V)
OPT
OPT
C332
0.47uF
50V
1.8V FPGA DDR SDRAM VTT & VREF
DDR_VTT
1V2
C310
C305
C307
22uF
22uF
22uF
16V
16V
16V
OPT
C331
C333
C336
22uF
0.1uF
22uF
16V
50V
16V
OPT
DDR_VREF0
C343
0.1uF
DDR_VREF1
16V
C342
0.1uF
16V
+1.8V_DDR
IC307
AP2132MP-2.5TRG1
[EP]
VOUT : 1.8
R348
PG
GND
10K
1
8
R351-*1
BCD
12K
BCD
R351
1%
R349
15K
R2
SEMTECH
EN
ADJ
R2
91K
2
7
R352-*1
SEMTECH
R352
15K
R1
1%
30K
SEMTECH
VIN
VOUT
BCD
R1
3
6
IC307-*1
SEMTECH
SC4215ISTRT
NC_1
1
8
GND
R350
VCTRL
NC
EN
2
7
ADJ
4
5
C390
VIN
3
6
VO
C389
NC_2
NC_3
4
5
0
10uF
10uF
BCD
16V
16V
C388
2.2uF
BCD
16V
1.8V DDR SDRAM POWER
+1.8V_DDRS
IC308
AP2132MP-2.5TRG1
[EP]
VOUT : 1.8
R357
PG
GND
10K
1
8
R360-*1
BCD
12K
BCD
R360
1%
R358
15K
R2
SEMTECH
EN
ADJ
R2
100K
2
7
R361-*1
SEMTECH
R361
15K
30K
R1
1%
SEMTECH
VIN
VOUT
BCD
R1
3
6
SEMTECH
IC308-*1
SC4215ISTRT
NC_1
GND
1
8
EN
2
7
ADJ
R359
VCTRL
NC
VIN
3
6
VO
4
5
C396
NC_2
NC_3
C395
4
5
0
10uF
10uF
BCD
16V
16V
C394
2.2uF
BCD
16V
VOUT=0.6*(R1+R2)/R2
1V8
IC306
AP2132MP-2.5TRG1
[EP]
VOUT : 1.8
R366
10K
PG
GND
1
8
R369-*1
BCD
12K
BCD
R369
1%
R367
15K
R2
SEMTECH
EN
ADJ
R2
91K
2
7
R370-*1
SEMTECH
R370
15K
R1
1%
30K
VIN
VOUT
SEMTECH
BCD
R1
3
6
IC306-*1
SEMTECH
SC4215ISTRT
NC_1
GND
1
8
R368
VCTRL
NC
EN
2
7
ADJ
4
5
C3003
VIN
3
6
VO
C3002
NC_2
NC_3
4
5
C3004
0
10uF
10uF
BCD
0.1uF
16V
16V
C3001
BCD
0.22uF
50V
1.8V FPGA DDR SDRAM POWER
IC309
C344
C347
BD35331F-E2
10uF
0.1uF
1V8
16V
16V
GND
VTT
1
8
EN
VTT_IN
2
7
VTTS
VCC
3
6
L311
R329
BLM18PG121SN1D
VREF
VDDQ
220
4
5
OPT
C363
C359
C346
C351
C358
10uF
2.2uF
0.1uF
0.1uF
0.1uF
25V
10V
16V
16V
16V
L312
BLM18PG121SN1D
C345
0.1uF
16V
3D + 240 FRC + TCON BOARD
2009. 11. 13
FRC & FPGA Power Block
3
LGE Internal Use Only
C391
0.1uF
C397
0.1uF
+3.3V
C367
0.1uF
16V
10

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