LG 55X6500-TD Service Manual page 52

DDR_VREF0
C1004 C1006 IC1001
0.1uF 470pF
16V 50V H5PS5162FFR-S6C
DDR_DQ[0]
DDR_A[12-0] VREF J2 G8 DQ0
DDR_DQ[1]
DQ1
G2
DDR_DQ[2]
DQ2
DDR_A[0] H7
A0 M8 DDR_DQ[3]
DQ3
DDR_A[1] H3
A1
M3 DQ4 DDR_DQ[4]
DDR_A[2] H1
A2
M7 DDR_DQ[5]
DDR_A[3] H9 DQ5
A3
N2 DDR_DQ[6]
DQ6
DDR_A[4] A4 F1
N8 DDR_DQ[7]
DQ7
DDR_A[5] F9
A5 N3 DDR_DQ[8]
DQ8
DDR_A[6] C8
A6
N7 DQ9 DDR_DQ[9]
DDR_A[7] C2
A7
P2 DDR_DQ[10]
DDR_A[8] D7 DQ10
A8
P8 DDR_DQ[11]
DDR_A[9] D3 DQ11
A9
P3 DDR_DQ[12]
DQ12
DDR_A[10] A10/AP D1
M2 DDR_DQ[13]
DQ13
DDR_A[11] D9
A11 P7 DDR_DQ[14]
DQ14
DDR_A[12] B1
A12
R2 DQ15 DDR_DQ[15]
B9 1V8
BA0
DDR_BA[0] L2
BA1
DDR_BA[1] L3 1V8
A1 VDD5
VDD4
DDR2_CLK E1 C1019
CK VDD3
J8 J9 100pF
CK VDD2 50V
K8 M9
/DDR2_CLK CKE VDD1
K2 R1
DDR2_CKE
ODT
DDR2_ODT K9
CS VDDQ10
/DDR_CS L8 A9
/DDR_RAS RAS K7 C1 VDDQ9
CAS VDDQ8
/DDR_CAS L7 C3
WE VDDQ7
/DDR_WE K3 C7
VDDQ6
C9
VDDQ5
R1002 33 E9
LDQS
DDR_LDQS[0] F7
G1 VDDQ4
UDQS
DDR_UDQS[0] B7
VDDQ3
G3
R1003 33
VDDQ2
G7
LDM VDDQ1
DDR_LDM[0] F3 G9
UDM
DDR_UDM[0] B3
R1004 1K
LDQS VSS5
E8 A3
UDQS VSS4
A8 E3
R1005 1K J3 VSS3
VSS2
NC4 N1
L1
VSS1
P9
NC5 R3
NC6
R7
VSSQ10
B2
NC1 A2
VSSQ9
B8
NC2
E2 VSSQ8
A7
NC3
R8
D2 VSSQ7
VSSQ6
D8
VSSQ5
VSSDL E7
J7
VSSQ4
F2
VSSQ3
F8
H2 VSSQ2
VDDL VSSQ1
J1 H8
1V8
C1002 C1003 C1005 C1007 C1008 C1010 C1012 C1013 C1014 C1015 C1016 C1017 C1018
C1001
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
10uF
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
16V
DDR_VREF0
C1009 C1011
0.1uF 470pF
16V 50V
IC1000
EP3C55F484C6N
AA12
CLK13
SDDR_DQ[15-0] AB12
CLK12
SDDR_DQ[14]
AA13
B4_IO[0]
SDDR_DQ[9]
AB13
B4_IO[1]
SDDR_DQ[8]
AA14
B4_IO[2]
SDDR_DQ[15] AB14
B4_IO[3]
V12
B4_IO[4]
SDDR_DQ[12]
W13
B4_IO[5]
Y13
DDR_UDQS[0] B4_IO[6]
SDDR_DQ[13] AA15
B4_IO[7]
SDDR_DQ[10] AB15
B4_IO[8]
SDDR_DQ[11]
U12
B4_IO[9]
Y14
/DDR_CAS B4_IO[10]
Y15
DDR_A[11] B4_IO[11]
AA16
DDR_LDM[0] B4_IO[12]
SDDR_DQ[4] AB16
B4_IO[13]
V13
DDR_LDQS[0] B4_IO[14]
W14
DDR_A[1] B4_IO[15]
U13
B4_IO[16]
SDDR_DQ[1] V14
B4_IO[17]
U14
DDR_A[9] B4_IO[18]
U15
/DDR_RAS B4_IO[19]
SDDR_DQ[3]
V15
B4_IO[20]
SDDR_DQ[6] W15
B4_IO[21]
T14
B4_IO[22]
SDDR_DQ[7]
T15
B4_IO[23]
SDDR_DQ[2]
AB18
B4_IO[24]
AA17
DDR_A[0] B4_IO[25]
AB17
DDR_A[2] B4_IO[26]
AA18
B4_IO[27]
AA19
DDR2_ODT B4_IO[28]
AB19
/DDR_CS B4_IO[29]
SDDR_DQ[0] W17
B4_IO[30]
Y17
DDR_A[4] B4_IO[31]
AA20
B4_IO[32]
SDDR_DQ[5]
AB20
B4_IO[33]
V16
B4_IO[34]
U16
DDR2_CLK B4_IO[35]
U17
/DDR2_CLK B4_IO[36]
T16
DDR_A[8] B4_IO[37]
R16
DDR_A[6] B4_IO[38]
R14
DDR_A[5] B4_IO[39]
R15
FPGA_VSYNC_1V8 B4_IO[40]
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2010 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
DDR_VREF1
IC1002
C1028 C1031
0.1uF 470pF
H5PS5162FFR-S6C
16V 50V
SDDR_DQ[15-0]
DDR_A[12-0]
VREF
J2
DDR_DQ[5] AR1001 SDDR_DQ[5]
DDR_DQ[2] SDDR_DQ[2] DDR_A[0]
A0
M8
DDR_DQ[0] SDDR_DQ[0] DDR_A[1]
A1
M3
DDR_DQ[7] 33 SDDR_DQ[7] DDR_A[2] A2
M7
DDR_A[3]
A3 N2
DDR_DQ[13] AR1002 SDDR_DQ[13] DDR_A[4]
A4
N8
DDR_DQ[10] SDDR_DQ[10] DDR_A[5]
A5
N3
DDR_DQ[8] SDDR_DQ[8] DDR_A[6]
A6
N7
DDR_DQ[15] 33 SDDR_DQ[15] DDR_A[7] A7
P2
DDR_A[8] A8
P8
AR1003
DDR_DQ[14] SDDR_DQ[14] DDR_A[9]
A9 P3
DDR_DQ[9] SDDR_DQ[9] DDR_A[10]
A10/AP
M2
DDR_DQ[12] SDDR_DQ[12] DDR_A[11]
A11
P7
DDR_DQ[11] SDDR_DQ[11] DDR_A[12]
33 A12
R2
AR1004
DDR_DQ[6] SDDR_DQ[6]
BA0
DDR_DQ[1] SDDR_DQ[1] DDR_BA[0] L2
BA1
DDR_DQ[3] SDDR_DQ[3] DDR_BA[1] L3
DDR_DQ[4] SDDR_DQ[4] DDR2_CLK
33
CK
J8
CK K8
/DDR2_CLK
CKE K2
DDR2_CKE
DDR2_ODT ODT K9
CS
/DDR_CS L8
RAS
/DDR_RAS K7
CAS
/DDR_CAS L7
WE
/DDR_WE K3
R1007 33 LDQS
DDR_LDQS[1] F7
DDR_UDQS[1] UDQS B7
R1008 33
LDM
DDR_LDM[1] F3
DDR_UDM[1] UDM B3
R1009 1K
LDQS E8
UDQS
A8
R1010 1K
NC4
L1
NC5
R3
NC6
R7
NC1
A2
NC2
E2
NC3
R8
VSSDL
J7
VDDL
J1
1V8
C1020 C1021 C1022 C1023 C1024 C1025 C1026 C1029 C1032 C1033 C1034 C1035 C1036
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
DDR_VREF1
C1027 C1030
0.1uF 470pF
16V 50V
IC1000
EP3C55F484C6N
V6
LVDS_STABLE_1V8 B3_IO[0]
V5
DDR_LDM[1] B3_IO[1]
U7
SDDR_DQ[31-16] L/R_SYNC_1V8 B3_IO[2]
U8
3D_DIMMING_1V8 B3_IO[3]
Y4
/DDR_WE B3_IO[4]
SDDR_DQ[20] Y3
B3_IO[5]
Y6
DDR_BA[0] B3_IO[6]
AA3
DDR2_CKE B3_IO[7]
AB3
DDR_BA[1] B3_IO[8]
SDDR_DQ[22] W6
B3_IO[9]
V7
B3_IO[10]
SDDR_DQ[19]
AA4
B3_IO[11]
AB4
B3_IO[12]
SDDR_DQ[17]
AA5
B3_IO[13]
AA6
DDR_A[10] B3_IO[14]
AB6
B3_IO[15]
AB5
B3_IO[16]
SDDR_DQ[21]
W7
B3_IO[17]
SDDR_DQ[18] Y7
B3_IO[18]
U9
DDR_A[3] B3_IO[19]
SDDR_DQ[23]
V8
B3_IO[20]
SDDR_DQ[16]
W8
B3_IO[21]
AA7
DDR_UDM[1] B3_IO[22]
SDDR_DQ[27] AB7
B3_IO[23]
SDDR_DQ[25] Y8
B3_IO[24]
T10
3D_DIMMING_2_1V8 B3_IO[25]
T11
FRAME_INFO_1V8 B3_IO[26]
V9
B3_IO[27]
V10
DDR_LDQS[1] B3_IO[28]
SDDR_DQ[26]
U10
B3_IO[29]
SDDR_DQ[30]
AA8
B3_IO[30]
SDDR_DQ[28]
AB8
B3_IO[31]
SDDR_DQ[31] AA9
B3_IO[32]
AB9
DDR_UDQS[1] B3_IO[33]
U11
B3_IO[34]
SDDR_DQ[29]
V11
B3_IO[35]
W10
DDR_A[12] B3_IO[36]
SDDR_DQ[24] Y10
B3_IO[37]
AA10
DDR_UDM[0] B3_IO[38]
AB10
DDR_A[7] B3_IO[39]
AA11
CLK15
AB11
CLK14
SDDR_DQ[31-16]
DDR_DQ[16] DDR_DQ[21] AR1005 SDDR_DQ[21]
DQ0
G8
DDR_DQ[17] DDR_DQ[18] SDDR_DQ[18]
DQ1
G2
DQ2 DDR_DQ[18] DDR_DQ[16] SDDR_DQ[16]
H7
DDR_DQ[19] DDR_DQ[23] 33 SDDR_DQ[23]
H3 DQ3
DDR_DQ[20]
DQ4
H1
DDR_DQ[21] DDR_DQ[29] AR1006 SDDR_DQ[29]
DQ5
H9
DDR_DQ[22] DDR_DQ[26] SDDR_DQ[26]
DQ6
F1
DQ7 DDR_DQ[23] DDR_DQ[24] SDDR_DQ[24]
F9
DDR_DQ[24] DDR_DQ[31] 33 SDDR_DQ[31]
C8 DQ8
DDR_DQ[25]
DQ9
C2
DDR_DQ[26] DDR_DQ[30] AR1007 SDDR_DQ[30]
DQ10
D7
DDR_DQ[27] DDR_DQ[25] SDDR_DQ[25]
DQ11
D3
DDR_DQ[28] DDR_DQ[28] SDDR_DQ[28]
DQ12
D1
DQ13 DDR_DQ[29] DDR_DQ[27] 33 SDDR_DQ[27]
D9
DDR_DQ[30]
B1 DQ14
DDR_DQ[31] DDR_DQ[22] AR1008 SDDR_DQ[22]
DQ15
B9 1V8
DDR_DQ[17] SDDR_DQ[17]
DDR_DQ[19] SDDR_DQ[19]
DDR_DQ[20] 33 SDDR_DQ[20]
1V8
VDD5
A1
VDD4
E1
C1042
VDD3
J9 100pF
M9 VDD2 50V
R1 VDD1
VDDQ10
A9
VDDQ9
C1
VDDQ8
C3
VDDQ7
C7
C9 VDDQ6
VDDQ5
E9
VDDQ4
G1
VDDQ3
G3
VDDQ2
G7
VDDQ1
G9
A3 VSS5
VSS4
E3
VSS3
J3
VSS2
N1
VSS1
P9
B2 VSSQ10
B8 VSSQ9
VSSQ8
A7
VSSQ7
D2
VSSQ6
D8
VSSQ5
E7
F2 VSSQ4
VSSQ3
F8
VSSQ2
H2
VSSQ1
H8
DDR_VTT
C1037 C1038 C1039 C1040 C1041 C1043 C1044
DDR2_ODT DDR2_ODT
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
/DDR_CS /DDR_CS
16V 16V 16V 16V 16V 16V 16V
DDR_A[0] DDR_A[0]
DDR_A[2] DDR_A[2]
56 56
AR1009 AR1014
DDR_A[4] DDR_A[4]
DDR_A[6] DDR_A[6]
DDR_A[8] DDR_A[8]
DDR_A[11] DDR_A[11]
56 56
AR1010 AR1015
/DDR_CAS /DDR_CAS
/DDR_RAS /DDR_RAS
DDR_A[1] DDR_A[1]
DDR_A[5] DDR_A[5]
56 56
AR1011 AR1016
DDR_A[9] DDR_A[9]
DDR_A[12] DDR_A[12]
DDR_A[7] DDR_A[7]
DDR_A[3] DDR_A[3]
56 56
AR1012 AR1017
DDR_BA[0] DDR_BA[0]
DDR_BA[1] DDR_BA[1]
DDR2_CKE DDR2_CKE
/DDR_WE /DDR_WE
56 56
AR1013 AR1018
R1011 R1012
56 56
DDR_A[10] DDR_A[10]
DDR_VTT
C1045 C1048 C1051 C1054 C1056 C1058 C1060 C1062 C1064
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
16V 16V 16V 16V 16V 16V 16V 16V 16V
DDR_VTT
C1046 C1049 C1052 C1055 C1057 C1059 C1061 C1063
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
16V 16V
16V 16V 16V 16V 16V 16V
R1024
OPT
R1023
B
L/R_SYNC
10K
R1028
L/R_SYNC_FRC_OUT
10K
1V2 IC1000
2V5
EP3C55F484C6N
J11 D4
VCCINT[0] VCCIO1[0]
C1047 C1050 C1053 J12 F4 C1066 C1068 C1070
VCCINT[1] VCCIO1[1]
10uF 0.1uF 100pF 100pF 0.1uF 10uF
16V 16V 50V L14 K4 50V 16V 16V
VCCINT[2] VCCIO1[2]
M14
VCCINT[3]
P11 N4
VCCINT[4] VCCIO2[0]
P12 U4
VCCINT[5] VCCIO2[1]
1V8
L9 W4
VCCINT[6] VCCIO2[2]
M9
VCCINT[7]
J13 AB2
VCCINT[8] VCCIO3[0]
J14 W5 C1067 C1069 C1071
VCCINT[9] VCCIO3[1]
100pF 0.1uF 10uF
K14 W9 50V 16V 16V
VCCINT[10] VCCIO3[2]
J10 W11
VCCINT[11] VCCIO3[3]
K9
VCCINT[12]
N9
VCCINT[13]
AB21
VCCIO4[0]
P9
VCCINT[14]
W12
VCCIO4[1]
P10
VCCINT[15] W16
VCCIO4[2]
2V5
P13
VCCINT[16] W18
VCCIO4[3]
P14
VCCINT[17]
N14
VCCINT[18]
P18
VCCIO5[0]
J16
VCCINT[19]
V19
VCCIO5[1]
K15
VCCINT[20]
Y19
VCCIO5[2]
L16
VCCINT[21]
M15
VCCINT[22]
E19
VCCIO6[0]
R12
VCCINT[23]
G19
VCCIO6[1]
R10
VCCINT[24]
L19
VCCIO6[2]
R8
VCCINT[25]
H9
VCCINT[26]
A21
G12 VCCIO7[0]
VCCINT[27]
D12
VCCIO7[1]
J8
VCCINT[28]
D14
VCCIO7[2]
M8
VCCINT[29]
D16
VCCIO7[3]
T7
VCCINT[30]
T9
VCCINT[31]
T13 A2
VCCINT[32] VCCIO8[0]
P15 D5
VCCINT[33] VCCIO8[1]
H15 D9
VCCINT[34] VCCIO8[2]
H11 D11
VCCINT[35] VCCIO8[3]
K8
VCCINT[36]
L7
VCCINT[37]
1V2 2V5
C1072 C1077 C1082 C1087 C1092 C1097 C2002 C2007 C2012 C2016 C1074
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
16V 16V 16V 16V 16V 16V 16V 16V 16V 16V 16V
1V2
2V5
C1073 C1078 C1083 C1088 C1093 C1098 C2003 C2008 C2013
C1075
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
16V 16V 16V 16V 16V 16V 16V 16V 16V 0.1uF
16V
1V8
C1076
0.1uF
16V
3D Frame Info Level Shift (3.3V to 1.8V)
FPGA V-SYNC Level Shift (1.8V to 3.3V)
+3.3V 1V8
R1014 10K R1016 3.3K
R1017
22
FRAME_INFO_1V8
C
R1015
B Q1002
2SC3052
10K
E
C
R1013
B Q1001
3D_FRAME_INFO
2SC3052
10K
E
C1065
0.1uF
16V
R1018
FPGA_VSYNC_1V8
+3.3V 1V8
+3.3V 1V8
10K R1026 3.3K
R1030 R1032
10K 3.3K
R1027
OPT OPT R1033
22
22
L/R_SYNC_1V8
LVDS_STABLE_1V8
C
C
R1025 OPT
B Q1006
R1031
2SC3052 B Q1008
10K 2SC3052
10K
E OPT
OPT
C E
C
Q1005
R1029 B Q1007
2SC3052 FPGA_D/L_CTRL 3D_DIMMING_1V8
2SC3052
10K
OPT
E
OPT E
IC1000
EP3C55F484C6N
L10 C12
GND[0] GND[42]
L11 C14
GND[1] GND[43]
M10 C16
GND[2] GND[44]
M11 A22
GND[3] GND[45]
L12 E20
GND[4] GND[46]
L13 G20
GND[5] GND[47]
M12 L20
GND[6] GND[48]
M13 P19
GND[7] GND[49]
N11 V20
GND[8] GND[50]
K11 Y20
GND[9] GND[51]
N12 AB22
GND[10] GND[52]
K12 Y18
GND[11] GND[53]
K13 Y16
GND[12] GND[54]
N13 Y12
GND[13] GND[55]
N10 Y11
GND[14] GND[56]
K10 Y9
GND[15] GND[57]
J9 Y5
GND[16] GND[58]
F12 AB1
GND[17] GND[59]
H12 N3
GND[18] GND[60]
H13 U3
GND[19] GND[61]
J15 W3
GND[20] GND[62]
K16 D3
GND[21] GND[63]
L15 F3
GND[22] GND[64]
N15 K3
GND[23] GND[65]
R13
GND[24]
R11
GND[25]
R9
GND[26]
P8
GND[27]
H14
GND[28]
H10
GND[29]
H8
GND[30]
N8
GND[31]
R7
GND[32]
T8
GND[33]
T12
GND[34]
P16
GND[35]
L8
GND[36]
M7
GND[37]
A1
GND[38]
C5
GND[39]
C9
GND[40]
C11
GND[41]
C1079 C1084 C1089 C1094 C1099 C2004 C2009 C2014 C2017
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
16V 16V 16V 16V 16V 16V 16V 16V 16V
C1080 C1085 C1090 C1095 C2000 C2005 C2010 C2015 C2018
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
16V 16V 16V 16V 16V 16V 16V 16V 16V
C1081 C1086 C1091 C1096 C2001 C2006 C2011
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
16V 16V 16V 16V 16V 16V 16V
+3.3V +3.3V
R1019 R1021
10K 1K
R1022
22
FPGA_VSYNC
C
R1020
B Q1004
2SC3052
10K
E
C
B Q1003
2SC3052
10K
E
+3.3V +3.3V +3.3V +3.3V
R1035 R1037 R1040 R1042
10K 1K 10K 1K
R1038 R1043
22 22
3D_DIMMING
C C
R1036 R1041
B Q1010 B Q1012
2SC3052 2SC3052
10K 10K
E E
C C
R1034 B Q1009 R1039 B Q1011
3D_DIMMING_2_1V8
2SC3052 2SC3052
10K 10K
E E
3D + 240 FRC + TCON BOARD 2009. 11. 13
DDR2 10
LGE Internal Use Only
3D_DIMMING_2
10