Simultaneous Multithreading - IBM BladeCenter PS700 Technical Overview And Introduction

2.2.3 Simultaneous multithreading

An enhancement in the POWER7 processor is the addition of the SMT4 mode to enable four
instruction threads to execute simultaneously in each POWER7 processor core. Thus, the
instruction thread execution modes of the POWER7 processor are as follows:
SMT1: single instruction execution thread per core
SMT2: two instruction execution threads per core
SMT4: four instruction execution threads per core
SMT4 mode enables the POWER7 processor to maximize the throughput of the processor
core by offering an increase in processor-core efficiency. SMT4 mode is the latest step in an
evolution of multithreading technologies introduced by IBM. Figure 2-3 shows the evolution of
simultaneous multithreading.
Multi-threading Evolution
Figure 2-3 Evolution of simultaneous multithreading
The various SMT modes offered by the POWER7 processor allow flexibility, enabling users to
select the threading technology that meets an aggregation of objectives (such as
performance, throughput, energy use, and workload enablement).
Intelligent threads
The POWER7 processor features intelligent threads that can vary based on the workload
demand. The system either automatically selects (or the system administrator can manually
select) whether a workload benefits from dedicating as much capability as possible to a single
thread of work, or if the workload benefits more from having capability spread across two or
four threads of work. With more threads, the POWER7 processor can deliver more total
capacity as more tasks are accomplished in parallel. With fewer threads, workloads that need
fast individual tasks can get the performance they need for maximum benefit.
1995 Single thread out of order
FX0
FX1
FP0
FP1
LS0
LS1
B RX
C RL
2003 2 Way SMT
FX0
FX1
FP0
FP1
LS0
LS1
BR X
CR L
Thre ad 0 Ex ecuting
Thre ad 1 Ex ecuting
Thre ad 2 Ex ecuting
1997 Hardware muti-thread
FX0
FX1
FP0
FP1
LS0
LS1
B R X
C R L
2009 4 Way SMT
FX0
FX1
FP0
FP1
LS0
LS1
B RX
C RL
Thr ead 3 Exec uting
No Thre ad Ex ecuting
Chapter 2. Architecture and technical overview
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