Philips LC4.2E Service Manual page 69

Circuit Descriptions, Abbreviation List, and IC Data Sheets
7011
u-Processor
85 R_SDTV
G_SDTV
86
87 B_SDTV
HERCULES
IC
107 H_CS_SDTV
107 V_SDTV
PC-IN
6693 5686
5
15 DDC_5V
11 1
5
6
7694
7693
8 DDC
DDC_5V
8 DVI
NVM
NVM
1
2
DVI-IN
6
7
9
10
3,11,19,22
DDC_5V
5692
6691
3691
14
6692
3682
15
3710
16
17
18
23
24
9.7.1
Features
The Scaler provides several key IC functions:
•
Scaling.
•
Auto-configuration/ Auto-Detection.
•
Various Input Ports:
–
Analog RGB.
–
DVI Compliant.
–
Video Graphics.
•
Integrated LVDS Transmitter.
•
On-chip Micro-controller
9.7.2
Inputs
Analog RGB
The RGB input is fed to pins B2, C2 and D2. This input consists
of either the Hercules RGB output or the RGB/YpbPr input of
the VGA connector. The Scaler can switch between the two
signals via the PC_HD_SEL signal and selection IC SM5301.
PC (VGA) input
The VGA input is processed by the VGA block of the Scaler.
The Scaler supports pixel frequencies up to 165MHz.
YpbPr format is also supported via the VGA interface and
covers a resolution of 480p/560p/720p/1080i.
DVI-D input
The DVI-D input is processed by the Scaler and supports DVI
sources with a pixel clock frequency up to 81MHz.
7605
7604
A2 H_CS_SDTV
13
14 1 2 3 4 H_CS
A2 V_SDTV 1
HS
12
15
VS
2
6 9 8 V
5
9,11
A7 SD_HD_SEL
7607
A2 R_SDTV
27
SOG
A2 G_SDTV 3
17
R_PR+
A2 B_SDTV 7
14
RED_PR G_Y+
25
11
GRN_Y 1
B_PB+
BLU_PB
5
HD_FILTER 21
9
A7 SD_HD_SEL 22
7604-6
A7 PC_HD_SEL 13 12
HS
7604-5
6604
11 10 PC_HD_DET
VS
PC_HD_DET+
PC_HD_DET-
6605
7606
BLU_PB
1 2
GRN_Y
15 14
RED_PR 11 12
9, 17, 19
A 7
PC_HD_SEL
6
RX2-IN
RX2+IN
SCL_DVI
SDA_DVI
RX1-IN
RX1+IN
+5VSWI
HOT_PLUG
RX0-IN
RX0+IN
RXC+IN
RXC-IN
Figure 9-3 Block diagram Scaler Part
ANALOG
INPUT
PORT
A10
7501
ADDRESS
A7
DDR
FRAME
SDRAM
STORE
INTERFACE
DATA
DVI
INPUT
PORT
HOT_PLUG
GPIO_G07_B7
1401
2488
+3V3_PLL XTAL
2487
TCLK
9.7.3
Output
The Display Output Port provides data and control signals that
permit the Scaler to connect to a variety of display devices
using a TTL or LVDS interface. The output interface is
configurable for single or dual wide TTL/LVDS in 18, 24 or 30-
bit RGB pixels format. All display data and timing signals are
synchronous with the DCLK output clock. The integrated LVDS
transmitter is programmable to allow the data and control
signals to be mapped into any sequence depending on the
specified receiver format.
9.8
Video: Pixel Plus Part (diagram PP1 to PP4)
The Pixel Plus functionality is completely handled by an
Electronic Programmable Logic Device, EPLD (item 7101 on
diagram PP1, PP3). The LVDS output from the TV & Scaler
Board is fed trough a LVDS receiver (item 7201 on diagram
PP2) and then delivered to the EPLD. The EPLD processes the
signal and it is fed to the LCD panel via a LVDS transmitter
(item 7403 on diagram PP3).
The EPLD takes care of all picture improvement processing,
like:
•
Colour improvement
–
Blue stretch
–
Green enhancement
–
Saturation control
•
Sharpness enhancement
–
Non-linear horizontal peaking
–
Non-linear vertical peaking
–
Coring, clipping
LC4.2E AA 9.
ADDRESS
EXT.
FLASH
ROM
INTER-
FACE
DATA
7401
GM1501
SXGA DISPLAY
CONTROLLER
GRAPHIC
ZOOM
PAN_VCC
TXB0-
TXB3+
TXB0+
TXB3-
TXB1-
TXB1+
DISPLAY
TXBC+
TIMING
GEN
TXBC-
TXB2-
TXB2+
VIDEO
ZOOM
UART
INTERFACE
MICRO-
CONTROLLER
80186
INTERNAL
ROM &
RAM
EN 69
7530
FLASH
ROM
1403
1,2
3,4,5
6
7
8
9
10,11
12
14
15
13,16
17
18
19
20
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