Main(Op Drv) Schematic Diagram - JVC GR-D250US Schematic Diagrams

MAIN(OP DRV) SCHEMATIC DIAGRAM

0 1
VOI_CLK
TO CPU
VOI_OUT
VIDEO
VOI_IN
IRIS_CS
TO CPU
IRIS_PS
TO CPU,
T_F_V_RST
CDS/TG
IRIS_MCK
TO PARAGON VDIRS
HDIRS
TO CPU,
IR_OUT
MAIN IF(CN103)
REC_ADJ
TO MAIN IF ATF_GAIN
(CN104)
NOSIG_LV
DUMP_CTL
FSPLLCTL
TO PARAGON
M_VCOCTL
PBVCOCTL
TO VIDEO
ASPECT
TO CPU
LENS_LED
TO PARAGON VD_F/Z
TO CPU F/Z_CS
CAM_OUT
TO CPU,
CDS/TG
CAM_CLK
TO PARAGON
F/Z_MCK
TO CPU,
T_F_V_RST
CDS/TG
TO REG
REG_4.8V
M_REG4.8
REG_3.1V
GND
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
2-17(No.YF076)
MAIN(OP DRV)
L4902
10u
NQL38DK-100X
C4904
10/6.3
T
L4901
NQR0129-002X
C4902
10/6.3
T
R4935
100k
1 2 11 54 12
R4901
24k
C4906
0.1
R4903
8.2k
R4902
10k
80 43 79 42 78
46
3
R4944
0Ω
47
4
48
5
49
6
7
50
8
51
9
52
10
C4905
0.1
53
55 14 56 15 57
C4918 0.1
IC4901
JCY0215-X
13 22 63 23 24 33 72 34 35 44 45
C4909
C4910
R4904
0.01 OPEN
10k
R4908
4.7k
R4905
15k
C4908
C4907
0.1
0.1
R4910
R4906
100
680k C4911
R4911
100
CH
OPEN
41 77 40 39 76 38 75 37 74 36 73
IC4901
JCY0215-X
16 58 17 18 59 19 60 20 61 21 62
C4916 C4917
0.1 0.1
L4954
10u
NQL38DK-100X
C4952 C4951
10/6.3
T OPEN
L4953
NQR0129-002X
L4955
10u
NQL38DK-100X
OPEN
C4956 C4955
10/6.3 OPEN
T
71
32
70
31
CH
C4915
120p
69
C4914
R4923
R
68p
12k
CH
30
C
0
68
29
28
C4913
0.1
67
OPEN
R4912
C4920
100
27
66
R4945
10k
26
65
R4917 R4918
10k 10k
25
64
C4954 C4953
10/6.3 OPEN
T