Main(Reg) Schematic Diagram - JVC GR-D250US Schematic Diagrams

MAIN(REG) SCHEMATIC DIAGRAM

0 1 MAIN(REG)
TO MAIN IF(CN107)
BATT_CHK
BATT_+
TO MAIN IF(CN107)
ADP_DC
TO CPU
CHRG_EVR
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
2-19(No.YF076)
R6013
0Ω
L6002
L6001
OPEN
OPEN
! R6014
0Ω
F6001
NMFZ007-2R5X-K
C6003 C6005
OPEN
1
R6708
15k
C6704
0.0047
R6713
220k
R6715
4.7k
R6717
18k
C6707 R6718
820p 0Ω
C6509 R6512
0.033 47k
C6203 R6203
0.001 0Ω
R6709
110k
TL6001
C6703
R6710
OPEN
120k
R6711
OPEN
IN7-
FB7
R6712
560
IN6C-
FB6C
C6705 R6714
0.01 4.7k
IN6-
FB6
C6706 R6716
220p 8.2k
IN5-
FB5 IC6001
C6510 R6513
0.047 2.7k
IN4+
FA7725F
IN4-
C6405
0.01
FB4
IN3+
IN3-
C6305
0.1
FB3
IN2-
FB2
C6204 R6204
220p 8.2k
R6103
8.2k
C6103
220p
R6104 R6803
0Ω 1k
C6104
C6804
680p
0.0039
TL6002
IN12-
FB12
R6105 C6105
12k 0.01
OUT12
OUT11
OUT10
OUT7S
OUT6S
24k
OUT6P
OUT5P
OUT4P
OUT3P
OUT2N
OUT2P
OUT1N
OUT1P
PGND1
TL6003
R6006
0Ω
C6011
1
R6007
OPEN
D68
RB551V-3
L6801
47µ
NQL79GM-470X
C68
10
R6106
100k
S
Q6103
G
SSM3J14T-X
C65
0
D
C65
1
R6107 R6108
C610
1
_0.5%
36k _0.5%
C6107
0.022
R6110
3.3k