Main(Op Drv) Schematic Diagram - JVC GR-DA30UC Schematic Diagrams

MAIN(OP DRV) SCHEMATIC DIAGRAM

5 4
C4924
C4923 OPEN
OPEN
1 2 3 IC4902
MM1614GN-X
OPEN
C4927
OPEN
L4902
10u
REG_4.65V REG_4.65V_L4902
REG_4.65V
NQLC32M-100X
C4903
10/6.3
T
L4901
NQR0602-001X
REG_2.8V
REG_2.8V
C4904
10µ
C4902
10u
GND
L4904
NQL38DK-100X
C4935
10/6.3
T
L4903
10u
M_REG4.65
NQL38DK-100X
C4932
10/10
T
GND
H_OFFSET
H_GAIN
TO PARAGON3 OPDRV_VD
CLK27O
CLK27O
VDMDA
OPOSD_CLK
OPDRV_CS
OPOSD_OUT
TO CPU
OPOSD_IN
OPDRV_PS
OPOSD_RST
VD_FZ
0 1 MAIN(OP DRV)
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
IC4903
R1100D311C-X
OPEN
1 2 3
C4925 C4926
OPEN OPEN
REG_2.8V_L4901
R4962
120
C4936
OPEN
M_REG4.65_L4903
Q4901
RPM-22PB
N.C.
NT
GNDD
C4905
0.1
DVDD
RETB
SCK
TL4911 PLS3
TL4912 PLS4
TL4913 MONI0
TEST
CS
SIN
OSCIN
VD_IS
R4953
SOUT
470
PDWNB
R4925
OPEN
VD_FZ
R4963 Ach Bch
PLS1
OPEN
TL4914 PLS2
MODESEL
OPEN
C4940
(No.YF219)2-19
BA10358FVM-W
IC4904 8 7 6 5
1 2 3 4
R4961
OPEN
C4942
C4941 0.1
O.1
R4955
R4954
10K
10K
R4906 R4907
560k
1M C4910
R4904 OPEN
R4905
10k
33k
C4909
R4903 0.01
8.2k
C4907
C4911
0.1 CH
100p
R4902
10K
C4901
0.1
R4912
10K
TL4915
R4911
100
RHTRIN
TEST2
MONI1 TL4916
IRISOUTA
GNDA
AVDD3
CH
DMP1
DMP0
R4960
OPEN
IC4901
R4924
120k
AN41904A-X
GND5A
C4913
0.1
AVDD5
C4937
OPEN
Cch Dch
N.C.
R4950
150K
C4921
0.022µ
(1005)
C4933
OPEN
OPEN
C4934
2-20(No.YF219)
C4912
0.1
C4916
0.1
R4920
6.8k
R4949
10K
yf219_y10718001a_rev0.1
ZOOM04
ZOOM03
ZOOM02
ZOOM01
F_VCC
DUMP+
DUMP-
DRIVE+
DRIVE-
HGVCC+
HGOUT+
TO MAIN IF(CN4901)
HGVSS-
HGOUT-
Z_LED
GND
FOCUS01
FOCUS04
FOCUS03
FOCUS02