Main(Op Drv) Schematic Diagram - JVC GZ-MG555US Schematic Diagrams

MAIN(OP DRV) SCHEMATIC DIAGRAM

5
C4923
1u
1 2 3
ND_DRV1
TO CPU
ND_DRV2
L4902
M_REG4.9 REG_4.9V_IC4901
TO MAIN IF M_REG4.9
NQL38DK-100X
(CN109)
L4901
NQR0154-004X
REG_3.1V
GND
L4904
NQL38DK-100X
OPEN
R4959
(1608)
L4903
M_REG4.9
TO MAIN IF M_REG4.9
NQL38DK-100X
(CN109)
GND
H_OFFSET
TO DSP H_GAIN
CLK27_CRS
TO PREPROCESS VDIRS
R4963
TO DSP,PREPROCESS CLK27_226
0R0
OPDRV_CLK
OPDRV_CS
OPDRV_OUT
TO CPU
OPDRV_IN
OPDRV_PS
OPDRV_RST
TO MAIN IF(CN113) IR_OUT
TO CPU VD_FZ
TO MAIN IF(CN109)
GATE_PLS
0 1 MAIN(OP DRV)
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
IC4903
IC4904
S-1112B29MC-W
LB1941T-X
4
5 4
C4924
1u
IC4902
C4919
MM1614GN-X
1 2 3 0.01
C4927
0.01u C4925
C4926
C4903
10/10
REG_3.1V_IC4901
C4902
10/10
C4917 C4918
10/10 0.01
C4935 C4936
10/10 0.01
C4932
10/10
N.C.
R4956
NT
0Ω
GNDD
C4905
0.1
DVDD
RETB
SCK
TL4002 PLS3
PLS4
TL4037
TL4020 MONI0
R4957
TEST
0Ω
CS
SIN
OSCIN
VD_IS
R4953
SOUT
470
PDWNB
VD_FZ
TL4030
PLS1 Ach
TL4043 PLS2
MODESEL
OPEN
C4940
(No.YF183)2-15
C4942
R4955
C4941 0.1u
R4954
0.1u
10K
10K
R4906
560k
R4907
1M
C4910
R4904 OPEN
R4905
10k
C4908 18k
C4909
R4903 0.1
0.01
8.2k
C4907
C4911
CH
0.1
100p
TL4038
RHTRIN
TEST2
MONI1
TL4051
IRISOUTA
GNDA
AVDD3
DMP1
DMP0
IC4901
AN41904A-X
GND5A
AVDD5
C4937
OPEN
Bch Cch Dch
N.C.
C4933
OPEN OPEN
C4934
2-16(No.YF183)
R4911
100
R4958
0Ω
C4912
0.1
CH
R4961
100K
R4962
R4924 12k
100k
C4943
0.1u
C4913
0.1
C4914
OPEN
C4916
0.1
R4920
68k
10K
150K R4949
R4950
0.047u
C4921
yf183_y10689001a_rev0.1
F_PTR_AD
Z_PTR_AD
TO CPU
OP_THRMO
GND
TO OP BLOCK
CN106
NRSA63J-202X
29 ZOOM04
28 ZOOM03
27 ZOOM02
26 ZOOM01
25 F_VCC
24 F_PTR_AD
23 F_LED
22 NC
21 DUMP+
20 DUMP-
19 DRIVE+
18 DRIVE-
17 HGVCC+
16 HGOUT-
15 HGVCC-
K216
14 HGOUT+
13 ND+
12 ND+
11 ND-
10 ND-
9 Z_PTR_AD
8 Z_LED
7 Z_VCC
6 OP_THRMO
5 GND
4 FOCUS01
3 FOCUS04
2 FOCUS03
1 FOCUS02